STA333BW STMicroelectronics, STA333BW Datasheet - Page 18

• Manufacturer Part Number: STA333BW
• Manufacturer: STMicroelectronics

Specifications of STA333BW

• Operational Class: Class-AB
• Audio Amplifier Output Configuration: 1-Channel Mono/2-Channel Stereo
• Audio Amplifier Function: Speaker
• Total Harmonic Distortion: 0.2@8Ohm@1W%
• Single Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (typ): 3.3/5/9/12/15/18V
• Power Supply Requirement: Quad
• Rail/rail I/o Type: No
• Power Supply Rejection Ratio: 80dB
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): 2.7/4.5V
• Dual Supply Voltage (max): 3.6/21.5V
• Operating Temp Range: -20C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 36
• Package Type: PowerSSO EP
• Lead Free Status / Rohs Status: Compliant

I
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5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.2
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C bus specification
I
The STA333BW supports the I
slave) and the output port SDA_OUT (slave to master). This protocol defines any device that
sends data on to the bus as a transmitter and any device that reads the data as a receiver.
The device that controls the data transfer is known as the master and the other as the slave.
The master always starts the transfer and provides the serial clock for synchronization. The
STA333BW is always a slave device in all of its communications. It supports up to 400 kb/s
(fast-mode bit rate).
For correct operation of the I
has a frequency at least 10 times higher than the frequency of the applied SCL clock.
Communication protocol
Data transition or change
Data changes on the SDA line must only occur when the clock SCL is low. A SDA transition
while the clock is high is used to identify a START or STOP condition.
Start condition
START is identified by a high to low transition of the data bus, SDA, while the clock, SCL, is
stable in the high state. A START condition must precede any command for data transfer.
Stop condition
STOP is identified by low to high transition of SDA while SCL is stable in the high state. A
STOP condition terminates communication between STA333BW and the bus master.
Data input
During the data input the STA333BW samples the SDA signal on the rising edge of SCL. For
correct device operation the SDA signal must be stable during the rising edge of the clock
and the data can change only when the SCL line is low.
Device addressing
To start communication between the master and the STA333BW, the master must initiate
with a start condition. Following this, the master sends onto the SDA line 8-bits (MSB first)
corresponding to the device select address and read or write mode bit.
The seven most significant bits are the device address identifiers, corresponding to the I
bus definition. In the STA333BW the I
the SA pin configuration, 0x38 when SA = 0, and 0x3A when SA = 1.
The eighth bit (LSB) identifies a read or write operation (R/W); this is set to 1 for read and to
0 for write. After a START condition the STA333BW identifies the device address on the SDA
bus and if a match is found, acknowledges the identification during the 9th bit time frame.
The byte following the device identification is the address of a device register.
2
C bus specification
2
C interface ensure that the master clock generated by the PLL
Doc ID 13773 Rev 3
2
C protocol via the input ports SCL and SDA_IN (master to
2
C interface has two device addresses depending on
STA333BW
2
C