ICS83940BY IDT, Integrated Device Technology Inc, ICS83940BY Datasheet
ICS83940BY
Specifications of ICS83940BY
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ICS83940BY Summary of contents
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G D ENERAL ESCRIPTION The ICS83940 is a low skew, 1-to-18 LVPECL-to-LVCMOS/ LVTTL Fanout Buffer. The ICS83940 has twoselectable clock inputs. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL ...
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ABLE IN ESCRIPTIONS ...
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BSOLUTE AXIMUM ATINGS Supply Voltage Inputs, V -0. Outputs, V -0. Package Thermal Impedance, θ JA Storage Temperature, T -65°C to 150°C STG T 4A ...
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T 5A ABLE HARACTERISTICS ...
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T 4D ABLE HARACTERISTICS ...
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P ARAMETER 1.65V± DDx LVCMOS GND -1.65V±5% 3. UTPUT OAD EST IRCUIT V DD nPCLK V Cross Points PP PCLK GND IFFERENTIAL NPUT EVEL PART 1 V DDx ...
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IRING THE IFFERENTIAL NPUT TO Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors R1, R2 and C1. This bias ...
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LVPECL LOCK NPUT NTERFACE The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both V and V SWING and V input requirements. Figures show interface CMR examples for the PCLK/nPCLK input driven ...
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ABLE VS IR LOW ABLE FOR JA θ θ θ θ θ Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The ...
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ACKAGE UTLINE UFFIX FOR ABLE ACKAGE ...
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ABLE RDERING NFORMATION ...
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We’ve Got Your Timing Solution. 6024 Silver Creek Valley Road San Jose, CA 95138 © 2010 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of ...