ICS8521AYI-03 IDT, Integrated Device Technology Inc, ICS8521AYI-03 Datasheet - Page 9

• Manufacturer Part Number: ICS8521AYI-03
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Driverr

Specifications of ICS8521AYI-03

• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 500MHz
• Output Logic Level: LVHSTL
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: LQFP
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / Rohs Status: Not Compliant

P
This section provides a layout guide related to power, ground
and placement of bypass capacitors for a high-speed digital IC.
This layout guide is a general recommendation. The actual board
design will depend on the component types being used, the board
density and cost constraints. This description assumes that the
board has clean power and ground planes. The goal is to mini-
mize the ESR between the clean power/ground plane and the
IC power/ground pin. A low ESR bypass capacitor should be
used on each power pin. The value of bypass capacitors ranges
from 0.01uF to 0.1uF. The bypass capacitors should be located
8521AYI-03
OWER
1.8V
, G
LVHSTL Driv er
ROUND AND
Zo = 50 Ohm
Zo = 50 Ohm
B
F
YPASS
IGURE
R9
50
3B. R
VDD=3.3V
C
APACITOR
R10
50
ECOMMENDED
VDD=3.3V
R12 1K
R11
C5
0.1u
1K
U1
ICS8521I-03
L
1
2
3
4
5
6
7
8
www.idt.com
VDDO=1.8V
AYOUT OF
C1
0.1u
C3
0.1u
VDD
CLK0
nCLK0
CLK_SEL
CL:K1
nCLK1
GND
CLK_EN
9
as close to the power pin as possible. It is preferable to locate
the bypass capacitor on the same side as the IC. Figure 3B
shows suggested capacitor placement. Placing the bypass ca-
pacitor on the same side as the IC allows the capacitor to
have direct contact with the IC power pin. This can avoid any
vias between the bypass capacitor and the IC power pins. The
vias should be placed at the Power/Ground pads. There should
be a minimum of one via per pin. Increasing the number of vias
from the Power/Ground pads to Power/Ground planes can im-
prove the conductivity
D
IFFERENTIAL
B
YPASS
C
VDDO
VDDO
VDDO=1.8V
APACITOR
nQ3
nQ4
nQ5
C4
0.1u
VDDO=1.8V
Q3
Q4
Q5
C2
0.1u
24
23
22
21
20
19
18
17
-
TO
P
-LVHSTL F
LACEMENT
C7
0.1u
Zo = 50
Zo = 50
C6
0.1u
Zo = 50
Zo = 50
ICS8521I-03
L
OW
R2
50
R8
50
ANOUT
S
KEW
R1
50
REV. B JULY 26, 2010
R7
50
+
-
+
-
, 1-
B
UFFER
TO
-9