MC68HC811E2FN Freescale Semiconductor, MC68HC811E2FN Datasheet - Page 138
MC68HC811E2FN
Manufacturer Part Number
MC68HC811E2FN
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC811E2FN.pdf
(242 pages)
Specifications of MC68HC811E2FN
Cpu Family
HC11
Device Core Size
8b
Frequency (max)
4MHz
Interface Type
SCI/SPI
Program Memory Type
ROMLess
Program Memory Size
Not Required
Total Internal Ram Size
256Byte
# I/os (max)
38
Number Of Timers - General Purpose
8
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3V
On-chip Adc
8-chx8-bit
Instruction Set Architecture
CISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
52
Package Type
PLCC
Lead Free Status / Rohs Status
Supplier Unconfirmed
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Timing Systems
9.4.7 Timer Interrupt Mask 1 Register
Use this 8-bit register to enable or inhibit the timer input capture and output compare interrupts.
OC1I–OC4I — Output Compare x Interrupt Enable Bits
I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable Bit
IC1I–IC3I — Input Capture x Interrupt Enable Bits
9.4.8 Timer Interrupt Flag 1 Register
Bits in this register indicate when timer system events have occurred. Coupled with the bits of TMSK1,
the bits of TFLG1 allow the timer subsystem to operate in either a polled or interrupt driven system. Each
bit of TFLG1 corresponds to a bit in TMSK1 in the same position.
Clear flags by writing a 1 to the corresponding bit position(s).
OC1F–OC4F — Output Compare x Flag
I4/O5F — Input Capture 4/Output Compare 5 Flag
IC1F–IC3F — Input Capture x Flag
138
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt sequence is requested.
When I4/O5 in PACTL is 1, I4/O5I is the input capture 4 interrupt enable bit. When I4/O5 in PACTL is
0, I4/O5I is the output compare 5 interrupt enable bit.
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested.
Set each time the counter matches output compare x value
Set by IC4 or OC5, depending on the function enabled by I4/O5 bit in PACTL
Set each time a selected active edge is detected on the ICx input line
Address:
Address:
Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Bits in TMSK1
enable the corresponding interrupt sources.
Reset:
Reset:
Read:
Read:
Write:
Write:
$1022
$1023
OC1F
Figure 9-17. Timer Interrupt Mask 1 Register (TMSK1)
OC1I
Bit 7
Bit 7
Figure 9-18. Timer Interrupt Flag 1 Register (TFLG1)
0
0
OC2F
OC2I
6
0
6
0
M68HC11E Family Data Sheet, Rev. 5.1
OC3F
OC3I
5
0
5
0
NOTE
OC4F
OC4I
4
0
4
0
I4/O5F
I4/O5I
3
0
3
0
IC1F
IC1I
2
0
2
0
IC2F
IC2I
1
0
1
0
Freescale Semiconductor
IC3F
Bit 0
Bit 0
IC3I
0
0
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