7130SA25PF IDT, Integrated Device Technology Inc, 7130SA25PF Datasheet - Page 12

• Manufacturer Part Number: 7130SA25PF
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 7130SA25PF

• Density: 8Kb
• Access Time (max): 25ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 10b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 2
• Supply Current: 220mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Word Size: 8b
• Number Of Words: 1K
• Lead Free Status / Rohs Status: Not Compliant

IDT7130SA/LA AND IDT7140SA/LA
HIGH-SPEED 1K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
TRUTH TABLES
TABLE I — NON-CONTENTION
READ/WRITE CONTROL
NOTES:
1. A
2. If
3. If
4. 'H' = V
TABLE II — INTERRUPT FLAG
NOTES:
1. Assumes
2. If
3. If
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
NOTES:
1. Pins
2. 'L' if the inputs to the opposite port were stable prior to the address and
3. Writes to the left port are internally ignored when
TABLE III — ADDRESS BUSY ARBITRATION
R/
R/
CE CE CE CE CE
X
X
H
H
L
inputs for IDT7140 (slave).
not push-pull outputs. On slaves the
enable inputs of this port. 'H' if the inputs to the opposite port became
stable after the address and enable inputs of this port. If tAPS is not met,
either
not be low simultaneously.
driving Low regardless of actual logic level on the pin. Writes to the right
port are internally ignored when
less of actual logic level on the pin.
W W W W W
X
H
X
L
0L
L
X
X
X
BUSY
BUSY
BUSY
BUSY
W W W W W
Left or Right Port
L
– A
L
BUSY
CE CE CE CE CE
IH
BUSY
H
H
L
L
L
10L
L
R
CE CE CE CE CE
, 'L' = V
= L, data is not written.
= L, data may not be valid, see t
= V
X
X
H
BUSY
= V
L
CE CE CE CE CE
Inputs
R
X
X
L
L
L
IL
L
IL
and
A
OE OE
OE OE
OE
L
, then No Change.
or
X
X
X
H
, then No Change.
L
0R
NO MATCH
IL
L
Left Port
A
BUSY
A
, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
=
BUSY
MATCH
MATCH
MATCH
– A
0R
0L
BUSY
DATA
OE OE
OE OE
OE
DATA
-A
-A
10R
X
X
X
L
D
R
R
9L
9R
(1)
L
Z
Z
Z
= Low will result.
0–7
are both outputs for IDT7130 (master). Both are
.
R
OUT
BUSY
= V
IN
BUSY
BUSY
BUSY
BUSY
BUSY
IH
A
Port Disabled and in Power-
Down Mode, I
CE
Mode, I
Data on Port Written Into Memory
Data in Memory Output on Port
High Impedance Outputs
9L
X
BUSY
(2)
3FE
3FF
H
H
H
outputs on the IDT7130 are open drain,
R
– A
X
X
BUSY
(4)
L
Outputs
=
(1)
R
0L
CE
WDD
SB1
outputs are driving Low regard-
BUSY
X
BUSY
BUSY
BUSY
BUSY
BUSY
L
input internally inhibits writes.
=
or I
and t
(2)
Function
H
H
H
V
(1,4)
INT
INT
INT
INT
INT
L
H
SB2
L
IH
SB3
and
X
X
R
(3)
(2)
DDD
, Power-Down
(1)
L
or I
BUSY
BUSY
timing.
Normal
Normal
Normal
Write Inhibit
SB4
R/
L
Function
R
X
X
X
L
W W W W W
outputs are
outputs can
R
2689 tbl 15
2689 tbl 13
(3)
CE CE CE CE CE
(3)
X
X
L
L
(2)
R
6.01
Right Port
OE
OE OE
OE OE
X
X
X
L
R
A
9L
MILITARY AND COMMERCIAL TEMPERATURE RANGES
3FE
3FF
– A
X
X
0R
INT
INT
INT
INT
INT
H
L
X
X
(2)
(3)
R
Set Right
Reset Right
Set Left
Reset Left
Function
INT
INT
INT
L
INT
R
Flag
L
Flag
R
Flag
Flag
2689 tbl 14
12