UDA1380HN NXP Semiconductors, UDA1380HN Datasheet - Page 45

• Manufacturer Part Number: UDA1380HN
• Manufacturer: NXP Semiconductors

Specifications of UDA1380HN

• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
Table 56 ADC input amplifier PGA gain setting bits
11.13 ADC settings
Table 57 Register address 22H
Table 58 Description of register bits
2004 Apr 22
Symbol
Default
Symbol
Default
PGA_GAINCTRLR3
PGA_GAINCTRLL3
15 to 13
Stereo audio coder-decoder
for MD, CD and MP3
11 to 8
11 to 8
7 to 4
3 to 0
BIT
BIT
BIT
BIT
12
0
0
0
0
0
0
0
0
1
PGA_GAIN
CTRLR[3:0]
−
PGA_GAIN
CTRLL[3:0]
−
ADCPOL_INV
VGA_CTRL[3:0] Microphone input VGA gain settings. A 4-bit value to program the gain of the LNA
15
−
0
7
−
0
SYMBOL
SYMBOL
14
−
0
6
−
0
PGA_GAINCTRLR2
PGA_GAINCTRLL2
13
−
0
5
−
0
ADC input amplifier right gain settings. A 4-bit value to program the gain of the
input amplifier. There are nine settings, for a gain range from 0 to 24 dB in steps of
3 dB. The gain control of the PGA is independent for left and right. Default value 0000,
see Table 56.
default value 0
ADC input amplifier left gain settings. A 4-bit value to program the gain of the input
amplifier. There are nine settings, for a gain range from 0 to 24 dB in steps of 3 dB.
The gain control of the PGA is independent for left and right. Default value 0000,
see Table 56.
default value 000
ADC polarity control. A 1-bit value to select ADC polarity. When this bit is logic 0:
polarity of ADC non-inverting. When this bit is logic 1: polarity of ADC inverting.
Default value 0.
in the microphone input channel. The range is 0 to 30 dB in steps of 2 dB.
Default value 0000, see Table 59.
X
0
0
0
0
1
1
1
1
ADCPOL_ INV VGA_CTRL3 VGA_CTRL2
12
0
4
−
0
PGA_GAINCTRLR1
PGA_GAINCTRLL1
SEL_LNA
45
X
0
0
1
1
0
0
1
1
11
0
3
0
DESCRIPTION
DESCRIPTION
SEL_MIC
PGA_GAINCTRLR0
PGA_GAINCTRLL0
10
0
2
0
X
0
1
0
1
0
1
0
1
VGA_CTRL1
SKIP_DCFIL
9
0
1
1
Product specification
PGA_GAIN (dB)
UDA1380
0 (default)
VGA_CTRL0
EN_DCFIL
12
15
18
21
24
3
6
9
8
0
0
0