AM29LV033C-90EI Spansion Inc., AM29LV033C-90EI Datasheet - Page 28

• Manufacturer Part Number: AM29LV033C-90EI
• Manufacturer: Spansion Inc.

Specifications of AM29LV033C-90EI

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 22b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 4M
• Supply Current: 16mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially de-
termines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
cles, determining the status as described in the previ-
ous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of
Table 10, on page 29
I on DQ6.
ure 19, on page 39
shows the toggle bit timing diagrams.
page 39
DQ6 in graphical form. See also the subsection on
“DQ2: Toggle Bit II” on page
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle
was not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously
programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the operation
has exceeded the timing limits, DQ5 produces a “1.”
Under both these conditions, the system must issue
the reset command to return the device to reading
array data.
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If addi-
tional sectors are selected for erasure, the entire
time-out also applies after each additional sector
erase command. When the time-out is complete, DQ3
switches from “0” to “1.” If the time between additional
sector erase commands from the system can be as-
sumed to be less than 50 µs, the system need not
monitor DQ3. See also
quence” on page
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data# Poll-
26
shows the differences between DQ2 and
Figure 6
23.
shows the toggle bit algorithm.
in the “AC Characteristics” section
shows the outputs for Toggle Bit
“Sector Erase Command Se-
27.
Figure 20, on
Figure
D A T A
6).
Am29LV033C
Fig-
S H E E T
ing) or DQ6 (Toggle Bit I) to ensure the device has ac-
cepted the command sequence, and then read DQ3. If
DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands (other than Erase Sus-
pend) are ignored until the erase operation is com-
plete. If DQ3 is “0”, the device accepts additional
sector erase commands. To ensure the command has
been accepted, the system software should check the
status of DQ3 prior to and following each subsequent
sector erase command. If DQ3 is high on the second
status check, the last command might not have been
accepted.
Notes:
1. Read toggle bit twice to determine whether or not it is
2. Recheck toggle bit because it may stop toggling as DQ5
toggling. See text.
changes to “1”. See text.
No
Figure 6. Toggle Bit Algorithm
Table 10
Complete, Write
Reset Command
Read DQ7–DQ0
Read DQ7–DQ0
Read DQ7–DQ0
Program/Erase
Operation Not
Toggle Bit
Toggle Bit
DQ5 = 1?
= Toggle?
= Toggle?
START
Twice
shows the outputs for DQ3.
Yes
Yes
Yes
22268B5 September 12, 2006
(Notes
1, 2)
(Note 1)
Operation Complete
No
No
Program/Erase