LRS1331C Sharp Electronics, LRS1331C Datasheet
LRS1331C
Specifications of LRS1331C
Related parts for LRS1331C
LRS1331C Summary of contents
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... Flash + 4M (x16) SRAM LRS1331C Date Dec. 11. 2001 ...
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Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe ...
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... Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 12.3 Write Cycle (F-WE Controlled 12.4 Write Cycle (F-CE Controlled 12.5 Block Erase, Full Chip Erase, Word Write and Lock-Bits Configuration Performance . . . . . . . . . . . . . . . . . . 17 12.6 Flash Memory AC Characteristics Timing Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 12.7 Reset Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 13. AC Electrical Characteristics for SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 13.1 AC Test Conditions ...
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... Description The LRS1331C is a combination memory organized as 1,048,576 16 bit flash memory and 262,144 16 bit static RAM in one package. Features - Power supply - Operating temperature - Not designed or rated as radiation hardened - 72 pin CSP (LCSP072-P-0811) plastic package - Flash memory has P-type bulk silicon, and SRAM has P-type bulk silicon ...
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Pin Configuration INDEX (TOP View) 3 Rev. 1.00 ...
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... Block Erase and Write Suspend : High-Z (High impedance Data Inputs and Outputs (Common F-V Power Supply (Flash) CC S-V Power Supply (SRAM) CC Write, Erase Power Supply (Flash) Block Erase and Write : F-V F-V CCW All Blocks Locked : F-V GND GND (Common) NC Non Connection Test pins (Should be all open) ...
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... V CCW CCWH Block erase, full chip erase, word write, or lock-bit configuration with F-V spurious results and should not be attempted. 3. Never hold F-OE low and F-WE low at the same timing. 4. Refer Section 5. Command Definitions for Flash Memory valid D 5. F-WP set ...
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Block Diagram Rev. 1.00 ...
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... Command Definitions for Flash Memory 5.1 Command Definitions Bus Cycles Command Read Array / Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Full Chip Erase Word Write Block Erase and Word Write Suspend Block Erase and Word Write ...
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Identifier Codes Codes Manufacture Code Device Code (2) Block Lock Configuration (2) Permanent Lock Configuration Notes selects the specific block lock configuration code to be read are reserved for future use. 15 ...
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Status Register Definition WSMS BESS ECBLBS 7 6 SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS Block Erase Suspended 0 = Block Erase in Progress/Completed ...
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... Memory Map for Flash Memory Rev. 1.00 ...
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Absolute Maximum Ratings Symbol Parameter V Supply voltage CC V Input voltage IN T Operating temperature A T Storage temperature STG F-V F-V voltage CCW CCW Notes: 1. The maximum applicable voltage on any pins with respect to GND. ...
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DC Electrical Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I F-V Standby Current CCS CC I F-V Auto Power-Save Current CCAS CC I F-V Reset Power-Down Current CCD CC I F-V Read ...
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Symbol Parameter I S-V Operation Current CC1 CC I S-V Operation Current CC2 CC V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH F-V Lockout during Normal CCW V ...
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... AC Electrical Characteristics for Flash Memory 12.1 AC Test Conditions Input pulse level Input rise and fall time Input and Output timing Ref. level Output load 12.2 Read Cycle Symbol t Read Cycle Time AVAV t Address to Output Delay AVQV t F-CE to Output Delay ELQV ...
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... Read timing characteristics during block erase, full chip erase, word write and lock-bit configurations are the same as during read-only operations. Refer to AC Characteristics for read cycle. 2. Sampled, not 100% tested. 3. Refer to Section 5. Command Definitions for Flash Memory for valid A write or lock-bit configuration. 4. F-V ...
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... In systems where F-CE defines the write pulse width (within a longer F-WE timing waveform), all setup, hold and inactive F-WE times should be measured relative to the F-CE waveform. 2. Sampled, not 100% tested. 3. Refer to Section 5. Command Definitions for Flash Memory for valid A write or lock-bit configuration. 4. F-V ...
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Block Erase, Full Chip Erase, Word Write and Lock-Bits Configuration Performance Symbol t WHQV1 Word Write Time t EHQV1 Block Write Time t WHQV2 Block Erase Time t EHQV2 Full Chip Erase Time t WHQV3 Set Lock-Bit Time t ...
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... Flash Memory AC Characteristics Timing Chart Read Cycle Timing Chart Rev. 1.00 ...
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Write Cycle Timing Chart (F-WE Controlled Rev. 1.00 ...
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Write Cycle Timing Chart (F-CE Controlled Rev. 1.00 ...
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Reset Operations Symbol F-RP Pulse Low Time t PLPH (If F-RP is tied this specification is not applicable.) CC F-RP Low to Reset during Block Erase, Full Chip Erase, Word t PLRZ Write or lock-bit ...
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AC Electrical Characteristics for SRAM 13.1 AC Test Conditions Input pulse level Input rise and fall time Input and Output timing Ref. level Output load Note: 1. Including scope and socket capacitance. 13.2 Read Cycle Symbol t Read Cycle ...
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Write Cycle Symbol t Write cycle time WC t Chip enable to end of write CW t Address valid to end of write AW t Byte select time BW t Address setup time AS t Write pulse width WP ...
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SRAM AC Characteristics Timing Chart Read cycle timing chart Rev. 1.00 ...
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Write cycle timing chart (S-WE Controlled Rev. 1.00 ...
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Write cycle timing chart (S-CE Controlled Rev. 1.00 ...
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Wrire cycle timing chart (S-UB, S-LB Controlled Rev. 1.00 ...
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Data Retention Characteristics for SRAM Symbol Parameter V Data Retention Supply voltage CCDR I Data Retention Supply current CCDR t Chip enable setup time CDR t Chip enable hold time R Notes 1. Reference value 25°C, ...
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... Notes This product is a stacked CSP package that a 16M (x16) bit Flash Memory and a 4M (x16) bit SRAM are assembled into. - Supply Power Maximum difference (between F-V - Power Supply and Chip Enable of Flash Memory and SRAM S-CE should not be “low” and S-CE ...
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... Data Protection during voltage transition 3. Data protection thorough F-RP • When the F-RP is kept low during power up and power down sequence, write operation on the flash memory is disabled, write protecting all blocks. • For the details of F-RP control, refer to the specification. (See Chapter 12. AC Electrical Characteristics for ...
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... Design Considerations 1. Power Supply Decoupling To avoid a bad effect to the system by flash memory power switching characteristics, each device should have a 0.1µF ceramic capacitor connected between its F-V inductance capacitors should be placed as close as possible to package leads. 2. F-V Trace on Printed Circuit Boards CCW ...
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... Memory“ described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page. Figure A-1. AC Timing at Device Power- the figure, refer to the next page. See the “AC Electrical Characteristics for Flash F i Rev. 1.10 ...
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A-1.1.1 Rise and Fall Time Symbol t F-V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device ...
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A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...