CY7C4265-15ASC Cypress Semiconductor Corp, CY7C4265-15ASC Datasheet - Page 11

• Manufacturer Part Number: CY7C4265-15ASC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4265-15ASC

• Configuration: Dual
• Density: 288Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 16Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 45mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Not Compliant

Switching Waveforms
Document #: 38-06004 Rev. *E
Notes
22. PAE offset − n.
23. t
24. If a read is preformed on this rising edge of the read clock, there are Empty + (n−1) words in the FIFO when PAE goes LOW.
25. PAF offset = m. Number of data words written into FIFO already = 8192 − (m + 1) for the CY7C4255 and 16384 − (m + 1) for the CY7C4265/65A.
26. PAF is offset = m.
27. 8192 − m words in CY7C4255 and 16384 – m words in CY7C4265/65A.
28. 8192 − (m + 1) words in CY7C4255 and 16384 – (m + 1) CY7C4265/65A.
WCLK and the rising RCLK is less than t
SKEW3
PAF
WEN2
WCLK
WCLK
RCLK
RCLK
WEN
WEN
REN
PAE
REN
[26]
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of
Figure 11. Programmable Almost Empty Flag Timing (applies only in SMODE (SMODE is LOW))
t
CLKH
(continued)
t
SKEW3
SKEW3
Figure 12. Programmable Almost Full Flag Timing
t
CLKH
t
t
ENS
ENS
, then PAE may not change state until the next RCLK.
[23]
t
t
ENH
ENH
t
CLKL
Note
Note
22
t
ENS
25
t
ENH
t
PAE synch
t
CLKL
t
PAF
CY7C4255, CY7C4265, CY7C4265A
t
t
ENS
ENS
FULL– M WORDS
N + 1 WORDS
INFIFO
INFIFO
t
ENS
[27]
t
PAF
t
ENH
FULL– (M+1) WORDS
Note
24
IN FIFO
t
PAE synch
[28]
Page 11 of 23
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