CY7C1380CV25-167AC Cypress Semiconductor Corp, CY7C1380CV25-167AC Datasheet - Page 9

• Manufacturer Part Number: CY7C1380CV25-167AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1380CV25-167AC

• Density: 18Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 2.5V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 275mA
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05240 Rev. *C
CY7C1382CV25–Pin Definitions
GW
BWE
CLK
CE
CE
CE
OE
ADV
ADSP
ADSC
Name
1
2
3
[2]
[2]
TQFP
88
87
89
98
97
92
86
83
84
85
BGA
M4
H4
K4
E4
G4
A4
P4
F4
-
-
(continued)
fBGA
B7
A7
B6
A3
B3
A6
B8
A9
B9
A8
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Asynchronou
Synchronous
Synchronous
Synchronous
Input-
Input-
Input-
Clock
Input-
Input-
Input-
Input-
Input-
Input-
Input-
I/O
s
Global Write Enable Input, active LOW.
When asserted LOW on the rising edge of
CLK, a global write is conducted (ALL bytes
are written, regardless of the values on BW
and BWE).
Byte Write Enable Input, active LOW.
Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
Clock Input. Used to capture all synchronous
inputs to the device. Also used to increment the
burst counter when ADV is asserted LOW,
during a burst operation.
Chip Enable 1 Input, active LOW. Sampled
on the rising edge of CLK. Used in conjunction
with CE
device. ADSP is ignored if CE
Chip Enable 2 Input, active HIGH. Sampled
on the rising edge of CLK. Used in conjunction
with CE
device.
Chip Enable 3 Input, active LOW. Sampled
on the rising edge of CLK. Used in conjunction
with CE
device. Not available for AJ package
version. Not connected for BGA. Where refer-
enced, CE
document for BGA.
Output Enable, asynchronous input, active
LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs.
When deasserted HIGH, I/O pins are
three-stated, and act as input data pins. OE is
masked during the first clock of a read cycle
when emerging from a deselected state.
Advance Input signal, sampled on the
rising edge of CLK, active LOW. When
asserted, it automatically increments the
address in a burst cycle.
Address Strobe from Processor, sampled
on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to
the device are captured in the address
registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is
ignored when CE
Address Strobe from Controller, sampled
on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to
the device are captured in the address
registers. A1: A0 are also loaded into the burst
counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
2
1
1
and CE
and CE
and CE
3
is assumed active throughout this
Description
2
3
3
1
CY7C1380CV25
CY7C1382CV25
to select/deselect the
to select/deselect the
to select/deselect the
is deasserted HIGH.
1
is HIGH.
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