CY7C1380CV25-167AC Cypress Semiconductor Corp, CY7C1380CV25-167AC Datasheet - Page 8

• Manufacturer Part Number: CY7C1380CV25-167AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1380CV25-167AC

• Density: 18Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 2.5V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 275mA
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05240 Rev. *C
CY7C1380CV25–Pin Definitions
CY7C1382CV25–Pin Definitions
V
MODE
TDO
TDI
TMS
TCK
NC
A
BW
DDQ
0
Name
Name
, A
A,
1
BW
, A
B
4,11,20,27,54,
37,36,32,
33,34,35,
42,43,44,
45,46,47,
48,49,50,
80,81,82,
14,16,66,
99,100
TQFP
93,94
TQFP
61,70,
39,38
77
31
-
-
-
-
A1,F1,J1,M1,U1,
A7,F7,J7,M7,U7
R1,T1,T2,J3,
L4,J5,R5,6T,
C2,R2,
P4,N4,
A2,B2,
T2,A3,
B3,C3,
T3,A5,
B5,C5,
T5,A6,
B6,C6,
R6,T6
G3,L5
BGA
B1,C1,
B7,C7,
BGA
D4,
6U,
R3
U5
U3
U2
U4
R7
(continued)
B2,B10,P3,P4,N6,P
R3,R4,R8,R9,R10,
E3,E9,F3,F9,G
C10,H1,H3,H9
N2,N5,N7,N10
,P1,A1,B11,P2
C3,C9,D3,D9,
L9,M3,M9,N3,
R6,P6,A2,
A11,B1,C2,
A10,A11,
P10,P11,
K3,K9,L3,
G9,J3,J9,
B5,A4
fBGA
8,P9,
,R2,N6
R11
fBGA
,H10,
N9
R1
P7
P5
R5
R7
3,
Synchronous
Synchronous
Synchronous
JTAG-Clock Clock input to the JTAG circuitry. If the JTAG
JTAG serial
JTAG serial
JTAG serial
I/O Power
Synchronous
Synchronous
Supply
output
Input-
Static
input
input
I/O
Input-
Input-
-
I/O
Power supply for the I/O circuitry.
Selects Burst Order. When tied to GND selects
linear burst sequence. When tied to V
floating selects interleaved burst sequence.
This is a strap pin and should remain static
during device operation. Mode Pin has an
internal pull-up.
Serial data-out to the JTAG circuit. Delivers
data on the negative edge of TCK. If the JTAG
feature is not being utilized, this pin should be
disconnected. This pin is not available on TQFP
packages.
Serial data-In to the JTAG circuit. Sampled on
the rising edge of TCK. If the JTAG feature is not
being utilized, this pin can be disconnected or
connected to V
TQFP packages.
Serial data-In to the JTAG circuit. Sampled on
the rising edge of TCK. If the JTAG feature is not
being utilized, this pin can be disconnected or
connected to V
TQFP packages.
feature is not being utilized, this pin must be
connected to V
TQFP packages.
No Connects. Not internally connected to the
die
Address Inputs used to select one of the
address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active
LOW, and CE
active. A1: A0 are fed to the two-bit counter. .
Byte Write Select Inputs, active LOW.
Qualified with BWE to conduct byte writes to
the SRAM. Sampled on the rising edge of CLK .
DD
DD
SS
1
, CE
Description
. This pin is not available on
. This pin is not available on
. This pin is not available on
Description
CY7C1380CV25
CY7C1382CV25
2
, and CE
3
are sampled
Page 8 of 33
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