CY7C1380CV25-167AC Cypress Semiconductor Corp, CY7C1380CV25-167AC Datasheet - Page 12

• Manufacturer Part Number: CY7C1380CV25-167AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1380CV25-167AC

• Density: 18Mb
• Access Time (max): 3.4ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 166MHz
• Operating Supply Voltage (typ): 2.5V
• Address Bus: 19b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 275mA
• Operating Supply Voltage (min): 2.375V
• Operating Supply Voltage (max): 2.625V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 512K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05240 Rev. *C
Write mechanism has been provided to simplify the Write
operations.
Because the CY7C1380CV25/CY7C1382CV25 is a common
I/O device, the Output Enable (OE) must be deserted HIGH
before presenting data to the DQs inputs. Doing so will
three-state the output drivers. As a safety precaution, DQs are
automatically three-stated whenever a Write cycle is detected,
regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write accesses are initiated when the following condi-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deserted HIGH, (3) CE
(4) the appropriate combination of the Write inputs (GW, BWE,
and BW
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into
the address register and the address advancement logic while
being delivered to the memory array. The ADV input is ignored
during this cycle. If a global Write is conducted, the data
presented to the DQs is written into the corresponding address
location in the memory core. If a Byte Write is conducted, only
the selected bytes are written. Bytes not selected during a
Byte Write operation will remain unaltered. A synchronous
self-timed Write mechanism has been provided to simplify the
Write operations.
Because the CY7C1380CV25/CY7C1382CV25 is a common
I/O device, the Output Enable (OE) must be deserted HIGH
before presenting data to the DQs inputs. Doing so will
three-state the output drivers. As a safety precaution, DQs are
automatically three-stated whenever a Write cycle is detected,
regardless of the state of OE.
Burst Sequences
The CY7C1380CV25/CY7C1382CV25 provides a two-bit
wraparound counter, fed by A1: A0, that implements either an
interleaved or linear burst sequence. The interleaved burst
sequence is designed specifically to support Intel Pentium
applications. The linear burst sequence is designed to support
ZZ Mode Electrical Characteristics
I
t
t
t
t
DDZZ
ZZS
ZZREC
ZZI
RZZI
Parameter
X
) are asserted active to conduct a Write to the desired
Snooze mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to snooze current
ZZ Inactive to exit snooze current
1
, CE
2
, CE
3
Description
are all asserted active, and
ZZ > V
ZZ < 0.2V
This parameter is sampled
ZZ > V
This parameter is sampled
processors that follow a linear burst sequence. The burst
sequence is user selectable through the MODE input.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
remain inactive for the duration of t
returns LOW.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Interleaved Burst Address Table
(MODE = Floating or VDD)
.
Linear Burst Address Table (MODE = GND)
Address
Address
Test Conditions
A1: A0
A1: A0
DD
DD
First
First
00
01
10
00
01
10
11
11
– 0.2V
– 0.2V
Address
Address
Second
Second
A1: A0
A1: A0
01
00
11
10
01
10
11
00
1
, CE
2
, CE
2t
Min.
CYC
0
CY7C1380CV25
CY7C1382CV25
Address
Address
3
A1: A0
A1: A0
, ADSP, and ADSC must
Third
Third
ZZREC
10
00
01
10
00
01
11
11
60mA
2t
2t
Max.
CYC
CYC
after the ZZ input
Page 12 of 33
Address
Address
Fourth
A1: A0
Fourth
A1: A0
11
10
01
00
11
00
01
10
Unit
mA
ns
ns
ns
ns
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