PA28F400BVB60 Intel, PA28F400BVB60 Datasheet - Page 26

• Manufacturer Part Number: PA28F400BVB60
• Manufacturer: Intel

Specifications of PA28F400BVB60

• Density: 4Mb
• Access Time (max): 60ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

4-MBIT SmartVoltage BOOT BLOCK FAMILY
3.5
3.5.1
With CE# at a logic-low level and RP# at a logic-
high level, the device is placed in the active mode.
Refer to the DC Characteristics table for I
values.
3.5.2
Automatic Power Savings (APS) provides low-
power operation during active mode.
Reduction Control (PRC) circuitry allows the device
to put itself into a low current state when not being
accessed. After data is read from the memory
array, PRC logic controls the device’s power
consumption by entering the APS mode where
typical I
stays in this static state with outputs valid until a
new location is read.
3.5.3
With CE# at a logic-high level (V
read mode, the memory is placed in standby mode,
which disables much of the device’s circuitry and
substantially reduces power consumption. Outputs
(DQ
impedance state independent of the status of the
OE# signal. When CE# is at logic-high level during
erase or program operations, the device will
continue to perform the operation and consume
corresponding active power until the operation is
completed.
3.5.4
The SmartVoltage boot block family supports a low
typical I
off all circuits to save power. This mode is activated
by the RP# pin when it is at a logic-low (GND
0.2 V). Note: BYTE# pin must be at CMOS levels to
meet the I
During read modes, the RP# pin going low de-
selects the memory and places the output drivers in
a high impedance state. Recovery from the deep
power-down state, requires a minimum access time
of t
26
PHQV
0
–DQ
CC
CC
(see the AC Characteristics table).
Power Consumption
15
CCD
ACTIVE POWER
AUTOMATIC POWER SAVINGS (APS)
STANDBY POWER
DEEP POWER-DOWN MODE
in deep power-down mode, which turns
current is less than 1 mA. The device
or DQ
specification.
0
–DQ
7
) are placed in a high-
IH
), and the CUI in
SEE NEW DESIGN RECOMMENDATIONS
CC
current
Power
During erase or program modes, RP# low will abort
either erase or program operations, but the memory
contents are no longer valid as the data has been
corrupted by the RP# function. As in the read mode
above, all internal circuitry is turned off to achieve
the power savings.
RP# transitions to V
device will clear the status register.
3.6
The device is protected against accidental block
erasure or programming during power transitions.
Power supply sequencing is not required, since the
device is indifferent as to which power supply, V
or V
mode after power-up, but the system must drop
CE# low or present a new address to ensure valid
data at the outputs.
A system designer must guard against spurious
writes when V
is active. Since both WE# and CE# must be low for
a command write, driving either signal to V
inhibit writes to the device. The CUI architecture
provides additional protection since alteration of
memory contents can only occur after successful
completion of the two-step command sequences.
The device is also disabled until RP# is brought to
V
holding the device in reset (RP# connected to
system PowerGood) during power-up/down, invalid
bus conditions during power-up can be masked,
providing yet another level of memory protection.
3.6.1
The use of RP# during system reset is important
with automated write/erase devices because the
system expects to read from the flash memory
when it comes out of reset. If a CPU reset occurs
without a flash memory reset, proper CPU
initialization would not occur because the flash
memory may be providing status information
instead of array data. Intel’s Flash memories allow
proper CPU initialization following a system reset
by connecting the RP# pin to the same RESET#
signal that resets the system CPU.
IH
, regardless of the state of its control inputs. By
CC
, powers-up first. The CUI is reset to the read
Power-Up/Down Operation
RP# CONNECTED TO SYSTEM
RESET
CC
voltages are above V
IL
, or turning power off to the
LKO
and V
IH
will
PP
PP