PA28F400BVB60 Intel, PA28F400BVB60 Datasheet - Page 17

• Manufacturer Part Number: PA28F400BVB60
• Manufacturer: Intel

Specifications of PA28F400BVB60

• Density: 4Mb
• Access Time (max): 60ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

3.2.2
To read the manufacturer and device codes, the
device must be in intelligent identifier read mode,
which can be reached using two methods: by
writing the Intelligent Identifier command (90H) or
by taking the A
identifier read mode, A
facturer’s identification code and A
device code. In byte-wide mode, only the lower byte
of the above signatures is read (DQ
“don’t care” in this mode). See Table 5 for product
signatures. To return to read array mode, write a
Read Array command (FFH).
Product
28F400
28F004
SEE NEW DESIGN RECOMMENDATIONS
Table 5. Intelligent Identifier Table
INTELLIGENT IDENTIFIERS
Mfr. ID
0089 H
89 H
9
pin to V
(Top Boot)
0
4470 H
78 H
= 0 outputs the manu-
-T
ID
. Once in intelligent
Device ID
0
= 1 outputs the
(Bottom Boot)
15
4471 H
79 H
/A
-B
–1
is a
4-MBIT SmartVoltage BOOT BLOCK FAMILY
3.3
3.3.1
The Command User Interface (CUI) is the interface
between the microprocessor and the internal chip
controller. Commands are written to the CUI using
standard
available
Intelligent Identifier, Read Status Register, Clear
Status Register, Erase and Program (summarized
in Tables 6 and 7). The three read modes are read
array, intelligent identifier read, and status register
read. For Program or Erase commands, the CUI
informs the Write State Machine (WSM) that a write
or erase has been requested. During the execution
of a Program command, the WSM will control the
programming sequences and the CUI will only
respond to status reads. During an erase cycle, the
CUI will respond to status reads and erase
suspend. After the WSM has completed its task, it
will set the WSM status bit to a “1” (ready), which
indicates that the CUI can respond to its full
command set. Note that after the WSM has
returned control to the CUI, the CUI will stay in the
current command state until it receives another
command.
3.3.1.1
Device operations are selected by writing specific
commands into the CUI. Tables 6 and 7 define the
available commands.
Write Operations
COMMAND USER INTERFACE (CUI)
commands
microprocessor
Command Function Description
are
write
Read
timings.
Array,
Read
The
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