LH28F640BFE-PBTL80 Sharp Electronics, LH28F640BFE-PBTL80 Datasheet - Page 27
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LH28F640BFE-PBTL80
Manufacturer Part Number
LH28F640BFE-PBTL80
Description
Manufacturer
Sharp Electronics
Datasheet
1.LH28F640BFE-PBTL80.pdf
(36 pages)
Specifications of LH28F640BFE-PBTL80
Cell Type
NOR
Density
64Mb
Access Time (max)
80ns
Interface Type
Parallel
Boot Type
Bottom
Address Bus
22b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
TSOP
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
16b
Number Of Words
4M
Supply Current
25mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Not Compliant
1.2.5 AC Characteristics - Write Operations
NOTES:
1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and
2. A write operation can be initiated and terminated with either CE# or WE#.
3. Sampled, not 100% tested.
4. Write pulse width (t
5. Write pulse width high (t
6. V
7. t
8. Refer to Table 6 for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AVAV
PHWL
ELWL
WLWH
DVWH
AVWH
WHEH
WHDX
WHAX
WHWL
SHWH
VVWH
WHGL
QVSL
QVVL
WHR0
OTP program operations are the same as during read-only operations. Refer to AC Characteristics for read-only
operations.
CE# or WE# (whichever goes high first). Hence, t
edge of CE# or WE# (whichever goes low last). Hence, t
program success (SR.1/3/4/5=0).
configuration.
WHR0
PP
Symbol
should be held at V
(t
(t
(t
(t
(t
(t
(t
(t
(t
(t
(t
(t
(t
WLEL
PHEL
EHR0
(t
AVEH
SHEH
EHWH
EHGL
ELEH
DVEH
EHDX
EHAX
VVEH
EHEL
EHR0
)
)
)
)
)
)
)
)
)
)
)
)
)
) after the Read Query or Read Identifier Codes/OTP command=t
Write Cycle Time
RST# High Recovery to WE# (CE#) Going Low
CE# (WE#) Setup to WE# (CE#) Going Low
WE# (CE#) Pulse Width
Data Setup to WE# (CE#) Going High
Address Setup to WE# (CE#) Going High
CE# (WE#) Hold from WE# (CE#) High
Data Hold from WE# (CE#) High
Address Hold from WE# (CE#) High
WE# (CE#) Pulse Width High
WP# High Setup to WE# (CE#) Going High
V
Write Recovery before Read
WP# High Hold from Valid SRD
V
WE# (CE#) High to SR.7 Going "0"
WP
PP
PP
) is defined from the falling edge of CE# or WE# (whichever goes low last) to the rising edge of
Setup to WE# (CE#) Going High
Hold from Valid SRD
PP
WPH
=V
) is defined from the rising edge of CE# or WE# (whichever goes high first) to the falling
PPH1/2
until determination of block erase, full chip erase, (page buffer) program or OTP
V
CC
Parameter
=2.7V-3.6V, T
WP
(1), (2)
LHF64FA3
=t
WLWH
WPH
A
=t
=t
=0 C to +70 C
WHWL
ELEH
=t
=t
WLEH
EHEL
=t
=t
ELWH
WHEL
AVQV
Notes
3, 6
3, 6
3, 7
3
4
8
8
5
3
3
.
+100ns.
=t
EHWL
.
Min.
150
200
80
50
40
50
30
30
0
0
0
0
0
0
0
t
AVQV
Max.
50
+
Rev. 2.44
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25