LH28F640BFE-PBTL80 Sharp Electronics, LH28F640BFE-PBTL80 Datasheet - Page 22
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LH28F640BFE-PBTL80
Manufacturer Part Number
LH28F640BFE-PBTL80
Description
Manufacturer
Sharp Electronics
Datasheet
1.LH28F640BFE-PBTL80.pdf
(36 pages)
Specifications of LH28F640BFE-PBTL80
Cell Type
NOR
Density
64Mb
Access Time (max)
80ns
Interface Type
Parallel
Boot Type
Bottom
Address Bus
22b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
TSOP
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
16b
Number Of Words
4M
Supply Current
25mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Not Compliant
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values are the reference values at V
2. I
3. Block erase, full chip erase, (page buffer) program and OTP program are inhibited when V
4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle
5. Sampled, not 100% tested.
6. V
7. The operating current in dual work is the sum of the operating current (read, erase, program) in each plane.
V
V
V
V
V
V
V
V
Symbol
IL
IH
OL
OH
PPLK
PPH1
PPH2
LKO
unless V
erase suspend mode, the device’s current draw is the sum of I
buffer) program suspend mode, the device’s current draw is the sum of I
in the range between V
completion. Standard address access timings (t
program cannot be executed and should not be attempted.
Applying 12V±0.3V to V
supplies the memory cell current for block erasing and (page buffer) programming. Use similar power supply trace widths
and layout considerations given to the V
Applying 12V±0.3V to V
may be connected to 12V±0.3V for a total of 80 hours maximum.
CCWS
PP
is not used for power supply pin. With V
and I
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
V
V
Erase, (Page Buffer) Program or OTP
Program Operations
V
Erase, (Page Buffer) Program or OTP
Program Operations
V
CC
Operations
PP
PP
PP
CC
is specified.
CCES
Lockout during Normal
Lockout Voltage
during Block Erase, Full Chip
during Block Erase, Full Chip
are specified with the device de-selected. If read or (page buffer) program is executed while in block
PPLK
Parameter
PP
PP
(max.) and V
provides fast erasing or fast programming mode. In this mode, V
during erase/program can only be done for a maximum of 1,000 cycles on each block. V
CC
PPH1
DC Characteristics (Continued)
power bus.
(min.), between V
AVQV
PP
Notes
3,5,6
V
V
) provide new data when addresses are changed.
5
5
5
5
6
6
LHF64FA3
CC
PPLK
=2.7V-3.6V
, block erase, full chip erase, (page buffer) program and OTP
V
Min.
1.65
11.7
-0.4
-0.2
2.4
1.5
CCQ
CCES
PPH1
and I
(max.) and V
Typ.
3.0
12
CCWS
CCR
V
or I
Max.
+ 0.4
and I
12.3
0.4
0.2
0.4
3.6
CCQ
CCW
PPH2
CCR
. If read is executed while in (page
(min.) and above V
.
Unit
V
V
V
V
V
V
V
V
PP
PP
V
CC
PPLK
V
V
I
V
V
I
is power supply pin and
OL
OH
CC
CCQ
CC
CCQ
=3.0V and T
=100 A
=-100µA
Test Conditions
=V
=V
, and not guaranteed
=V
=V
CC
CC
CCQ
CCQ
PPH2
Min.,
Min.,
Min.,
Min.,
Rev. 2.44
(max.).
A
=+25 C
20
PP