DT28F800F3B95 Intel, DT28F800F3B95 Datasheet - Page 21

• Manufacturer Part Number: DT28F800F3B95
• Manufacturer: Intel

Specifications of DT28F800F3B95

• Density: 8Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

4.9.1
4.9.2
PRELIMINARY
Read Configuration – (RCR.15)
The device supports two high performance read configurations: Synchronous burst mode and
asynchronous page mode. Bit RCR.15 in the read configuration register sets the read configuration
to either synchronous burst or asynchronous page mode. Asynchronous page mode is the default
read configuration state.
Parameter blocks, status register, and identifier modes only support single-synchronous and
asynchronous read operations.
Frequency Configuration Code Setting (FCC) – (RCR.13-11)
The frequency configuration code setting informs the device of the number of clocks that must
elapse after ADV# is driven active before data will be available. This value is determined by the
input clock frequency and the set up and hold requirements of the target system. See
“Frequency Configuration Settings” on page 17
codes. The frequency configuration codes in Table 7 are derived from equations (1), (2) and (3)
with assumed values for the t
calculation to obtain the frequency configuration code:
Flash performance can be determined by the following equations:
*
Parameters defined by CPU:
Parameters defined by flash:
Example:
CPU Clock Speed = 40 MHz
t
t
t
From Eq. (1):
From Eq. (2)
From Eq. (3)
The formula t
ADD
DATA
AVQV
Must use FCC = n - 1 when operating in the continous burst mode.
= 6 ns (typical speed from CPU) (max)
= 4 ns (typical speed from CPU) (min)
= 95 ns (from
{1/Frequency (MHz)} = CLK Period (ns)
n(CLK Period) t
n-2 = Frequency Configuration Code (FCC)
n : # of Clock periods (rounded up to the next integer)
t
t
t
Frequency Code Setting to the RCR is Code 3
ADD
DATA
AVQV
AVQV
= Clock to CE#, ADV#, or Address Valid whichever occurs last.
= Data set up to Clock
= Address to Output Delay
(ns) + t
Section 8.5
{1/40 (MHz)} = 25 ns
n(25 ns) 95 ns + 6 ns + 4 ns
n(25 ns) 105 ns
n 105/25 5 (Integer)
n - 2 = 5 - 2 = 3
ADD
AVQV
AVQV,
(ns) + t
AC Characteristic - Read Only Operations Table)
(ns) + t
t
ADD,
DATA
ADD
t
DATA
(ns) is also known as initial access time.
(ns) + t
for the specific input CLK frequency configuration
parameters. Below is the example of the
DATA
*
(ns)
28F800F3—Automotive
(1)
(2)
(3)
Table 7,
15