DT28F800F3B95 Intel, DT28F800F3B95 Datasheet - Page 20

• Manufacturer Part Number: DT28F800F3B95
• Manufacturer: Intel

Specifications of DT28F800F3B95

• Density: 8Mb
• Access Time (max): 95ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19b
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 16b
• Number Of Words: 512K
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

28F800F3—Automotive
4.9
14
RCR.15 = READ MODE (RM)
RCR.14 = RESERVED FOR FUTURE ENHANCEMENTS (R)
RCR.13–11 = FREQUENCY CONFIGURATION (FC2-0)
RCR.10 = RESERVED FOR FUTURE ENHANCEMENTS (R)
RCR.9 = DATA OUTPUT CONFIGURATION (DOC)
RCR.8 = WAIT CONFIGURATION (WC)
RCR.7 = BURST SEQUENCE (BS)
RCR.6 = CLOCK CONFIGURATION (CC)
RCR.5–3 = RESERVED FOR FUTURE ENHANCEMENTS (R) These bits are reserved for future use. Set these bits to “0.”
RCR.2–0 = BURST LENGTH (BL2–0)
0 = Synchronous Burst Reads Enabled
1 = page mode Reads Enabled (Default)
001 = Code 1 reserved for future use
010 = Code 2
011 = Code 3
100 = Code 4
101 = Code 5
110 = Code 6
0 = Hold Data for One Clock
1 = Hold Data for Two Clocks
0 = WAIT# Asserted During Delay
1 = WAIT# Asserted One Data Cycle Before Delay
0 = Intel Burst Order
1 = Linear Burst Order
0 = Burst Starts and Data Output on Falling Clock Edge
1 = Burst Starts and Data Output on Rising Clock Edge
001 = 4 Word Burst
010 = 8 Word Burst
111 = Continuous Burst
Table 6.
RM
BS
15
7
Read Configuration Register Definition
Set Read Configuration Command
The Set Read Configuration command writes data to the read configuration register. This operation
is initiated by a standard two bus cycle command sequence. The Read Configuration Setup
command (60H) is written and the data to be written to the read configuration is presented, which
is then followed by a second write that confirms the operation and again presents the data to be
written to the read configuration register. The read configuration register data is placed on the
address bus, A
(whichever occurs first). The read configuration register data sets the device’s read configuration,
burst order, frequency configuration, burst length and all other parameters. This command
functions independently of the applied V
returns to read array mode.
CC
14
R
6
15:0
FC2
,during both bus cycles and is latched on the rising edge of ADV#, CE#, or WE#
13
R
5
FC1
12
R
4
PP
NOTES:
Read mode configuration affects reads from main blocks.
Parameter block, status register, and identifier reads support
single read cycles.
These bits are reserved for future use. Set these bits to “0.”
See
configuration and its effect on the initial read.
Undocumented combinations of bits
RCR.14–11 are reserved by Intel Corporation for future
implementations and should not be used.
These bits are reserved for future use. Set these bits to “0.”
Undocumented combinations of bits RCR.10–9 are reserved
by Intel Corporation for future implementations and should not
be used.
In the asynchronous page mode, the burst length always
equals four words. Undocumented combinations of bits
RCR.2–0 are reserved by Intel Corporation for future
implementations and should not be used
voltage. After executing this command, the device
Section 4.9.2
FC0
11
R
3
for information about the frequency
BL2
10
R
2
DOC
BL1
9
1
PRELIMINARY
BL0
WC
8
0