PCF8576CT NXP Semiconductors, PCF8576CT Datasheet - Page 23

PCF8576CT

Manufacturer Part Number
PCF8576CT
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCF8576CT

Operating Supply Voltage (typ)
2.5/3.3/5V
Number Of Digits
20
Number Of Segments
160
Package Type
VSO
Pin Count
56
Mounting
Surface Mount
Power Dissipation
400mW
Frequency (max)
315KHz
Operating Supply Voltage (min)
2V
Operating Supply Voltage (max)
6V
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCF8576CT
Manufacturer:
NXP
Quantity:
3
Part Number:
PCF8576CT
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Part Number:
PCF8576CT/1
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
PCF8576CT/1
0
Company:
Part Number:
PCF8576CT/1
Quantity:
15 000
Part Number:
PCF8576CT/1,518
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Part Number:
PCF8576CT/1112
Manufacturer:
NXP Semiconductors
Quantity:
135
Part Number:
PCF8576CT/1118
Manufacturer:
NXPSemicondu
Quantity:
2 802
Part Number:
PCF8576CT/1Ј¬112
Manufacturer:
NXP
Quantity:
880
Part Number:
PCF8576CT/1Ј¬118
Manufacturer:
NXP
Quantity:
21 000
Part Number:
PCF8576CT/F1
Manufacturer:
PHILIPS/飞利浦
Quantity:
20 000
Part Number:
PCF8576CTT
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
8. Basic architecture
PCF8576C_9
Product data sheet
8.1.1.1 START and STOP conditions
8.1.1 Bit transfer
8.1.2 System configuration
8.1 Characteristics of the I
The I
modules. The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). When
connected to the output stages of a device, both lines must be connected to a positive
supply via a pull-up resistor. Data transfer is initiated only when the bus is not busy.
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse. Changes in the data line at this time will
be interpreted as a control signal. Bit transfer is illustrated in
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change
of the data line, while the clock is HIGH, is defined as the START condition (S).
A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP
condition (P). The START and STOP conditions are illustrated in
A device generating a message is a transmitter and a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves. The system configuration is illustrated in
Figure
Fig 14. Bit transfer
Fig 15. Definition of START and STOP conditions
2
C-bus provides bidirectional, two-line communication between different IC or
SDA
SCL
16.
START condition
SDA
SCL
S
Rev. 09 — 9 July 2009
2
C-bus
data valid
data line
stable;
Universal LCD driver for low multiplex rates
change
allowed
of data
Figure
STOP condition
Figure
mba607
PCF8576C
P
14.
© NXP B.V. 2009. All rights reserved.
15.
mbc622
SDA
SCL
23 of 56

Related parts for PCF8576CT