PCF8574P NXP Semiconductors, PCF8574P Datasheet - Page 12

PCF8574P

Manufacturer Part Number
PCF8574P
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCF8574P

Operating Temperature (min)
-40C
Operating Temperature Classification
Industrial
Operating Temperature (max)
85C
Package Type
PDIP
Rad Hardened
No
Lead Free Status / Rohs Status
Compliant

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7.2
The PCF8574 provides an open-drain output (INT) which
can be fed to a corresponding input of the microcontroller
(see Figs 13 and 14). This gives these chips a type of
master function which can initiate an action elsewhere in
the system.
An interrupt is generated by any rising or falling edge of the
port inputs in the input mode. After time t
valid.
Resetting and reactivating the interrupt circuit is achieved
when data on the port is changed to the original setting or
data is read from or written to the port which has generated
the interrupt.
Resetting occurs as follows:
2002 Nov 22
handbook, full pagewidth
handbook, full pagewidth
In the READ mode at the acknowledge bit after the rising
edge of the SCL signal
In the WRITE mode at the acknowledge bit after the
HIGH-to-LOW transition of the SCL signal
Remote 8-bit I/O expander for I
Interrupt output
DATA INTO
INT
P5
SDA
SCL
t iv
MICROCONTROLLER
start condition
S
Fig.14 Interrupt generated by a change of input to I/O P5.
INT
Fig.13 Application of multiple PCF8574s with interrupt.
0
1
slave address (PCF8574)
1
2
iv
0
3
the signal INT is
0
4
V DD
A2
5
2
C-bus
A1
6
PCF8574
A0
7
12
INT
(1)
R/W acknowledge
1
8
Each change of the I/Os after resetting will be detected
and, after the next rising clock edge, will be transmitted as
INT. Reading from or writing to another device does not
affect the interrupt circuit.
7.3
A quasi-bidirectional I/O can be used as an input or output
without the use of a control signal for data direction
(see Fig.15). At power-on the I/Os are HIGH. In this mode
only a current source to V
pull-up to V
outputs. These devices turn on when an output is written
HIGH, and are switched off by the negative edge of SCL.
The I/Os should be HIGH before being used as inputs.
Interrupts which occur during the acknowledge clock
pulse may be lost (or very short) due to the resetting of
the interrupt during this pulse.
A
from slave
t ir
PCF8574
Quasi-bidirectional I/Os
INT
(2)
DD
allows fast rising edges into heavily loaded
P5
1
data from port
DD
MBD976
PCF8574
is active. An additional strong
(16)
INT
Product specification
1
PCF8574
condition
MBD972
stop
P

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