HI-8686PQI Holt Integrated Circuits, HI-8686PQI Datasheet - Page 2

• Manufacturer Part Number: HI-8686PQI
• Manufacturer: Holt Integrated Circuits

Specifications of HI-8686PQI

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: TQFP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

PIN DESCRIPTIONS
FUNCTIONAL DESCRIPTION
The HI-8685 and HI-8686 are serial to 16-bit parallel con-
verters. The incoming data stream is serially shifted into an
input register, checked for errors, and then transferred in par-
allel to a 32-bit receive buffer. The receive data can be ac-
cessed using two 16-bit parallel read operations while the
next serial data steam is being received.
RECEIVER INPUTS
The block diagram for both the HI-8685 and HI-8685-10
products is found in Figure 1. Both have built-in receivers
eliminating the need for additional external ARINC level de-
tection circuitry. The only difference between the two prod-
ucts is the amount of internal resistance in series with each
ARINC input.
HI-8685 ARINC INPUTS (RINA & RINB)
Internal 35K
RINB ARINC 429 inputs. They connect to level translators
whose resistance to GND is typically 10K
RINA/RINA-10
RINB/RINB-10
PARITY ENB
DATA RDY
D0 to D15
GAPCLK
SIGNAL
ERROR
RESET
TESTA
TESTB
READ
GND
Vcc
W
resistors are in series with both the RINA and
FUNCTION
OUTPUT
OUTPUT
OUTPUT
POWER
POWER
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
Receiver data ready flag. A high level indicates data is available in the receive
buffer. Flag goes low when the first 16-bit byte is read.
16-bit parallel data bus (tri-state)
0V
Read strobe. A low level transfers receive buffer data to the data bus
Parity Enable - A high level activates odd parity checking which replaces the
32nd ARINC bit with an error bit. Otherwise, the 32nd ARINC bit is unchanged
Error Flag. A high level indicates a bit count error (number of ARINC bits was
less than or greater than 32) and/or a parity error if parity detection was enabled
(PARITY ENB high)
Positive direct ARINC serial data input
Negative direct ARINC serial data input (both RINB and RINB-10 on HI-8686)
Internal logic states are initialized with a low level
Used in conjunction with the TESTB input to bypass the built-in analog line
receiver circuitry
U
receiver circuitry
Gap Clock. Determines the minimum time required between ARINC words for
detection. The minimum word gap time is between 16 and 17 clock cycles of
this signal.
+5V ±5% supply
sed in conjunction with the TESTA input to bypass the built-in analog line
HOLT INTEGRATED CIRCUITS
W.
After level
HI-8685, HI-8686
2
translation, the buffered inputs drive a differential amplifier.
The differential signal is compared to levels derived from a
divider between VCC and GND. The nominal settings cor-
respond to a One/Zero amplitude of 6.0V and a Null ampli-
tude of 3.3V. A valid ARINC One/Zero input sets a latch and
a Null input resets the latch.
HI-8685-10 ARINC INPUTS (RINA-10 & RINB-10)
Since any added external series resistance will affect the
voltage translation, the HI-8685-10 product has only 25K
of the 35K
429 level detection. The remaining 10K
able to the user for incorporation in external circuitry such as
for lightning protection.
HI-8686 ARINC INPUTS
The HI-8686 has both sets of ARINC inputs, RINA/RINA-10
and RINB/RINB-10 available to the user.
DESCRIPTION
W
(both RINA and RINA-10 on HI-8686)
series resistance required for proper ARINC
W
required is avail-
W