PPC440GX-3NF667C Applied Micro Circuits Corporation, PPC440GX-3NF667C Datasheet - Page 78

• Manufacturer Part Number: PPC440GX-3NF667C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440GX-3NF667C

• Family Name: 440GX
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.55/2.5V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.5/2.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 552
• Package Type: FCBGA
• Lead Free Status / Rohs Status: Compliant

440GX – Power PC 440GX Embedded Processor
78
DDR SDRAM I/O Specifications
The DDR SDRAM controller times its operation with internal PLB clock signals and generates MemClkOut0 from
the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut0 is the
same frequency as the PLB clock signal and is in phase with the PLB clock signal.
Note: MemClkOut0 can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR program-
In the following sections, the label MemClkOut0(0) refers to MemClkOut0 when it has not been phase-shifted, and
MemClkOut0(90) refers to MemClkOut0 when it has been phase-advanced 90°. Advancing MemClkOut0 by 90°
creates a 3/4 cycle setup time and 1/4 cycle hold time for the address and control signals in relation to
MemClkOut0(90). The rising edge of MemClkOut0(90) aligns with the first rising edge of the DQS signal.
The following DDR data is generated by means of simulation and includes logic, driver, package RLC, and lengths.
Values are calculated over best case and worst case processes with speed, temperature, and voltage as follows:
Best Case = Fast process, -40°C, +1.6V
Worst Case = Slow process, +85°C, +1.4V
Note: In all the following DDR tables and timing diagrams, minimum values are measured under best case condi-
tions and maximum values are measured under worst case conditions.
The signals are terminated as indicated in the figure below for the DDR timing data in the following sections.
DDR SDRAM Simulation Signal Termination Model
Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.
ming register. In a typical system, users advance MemClkOut by 90°. This depends on the specific applica-
tion and requires a thorough understanding of the memory system in general (refer to the DDR SDRAM
controller chapter in the PowerPC 440GX User’s Manual).
PPC440GX
It is not a recommended physical circuit design for this interface. An actual interface design will depend on many
factors, including the type of memory used and the board layout.
Addr/Ctrl/Data/DQS
MemClkOut0
MemClkOut0
10pF
10pF
V
120Ω
TT
30pF
50Ω
= SV
DD
/2
Revision 1.20 – June 9, 2009
Data Sheet
AMCC