PPC440GX-3NF667C Applied Micro Circuits Corporation, PPC440GX-3NF667C Datasheet - Page 55

• Manufacturer Part Number: PPC440GX-3NF667C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440GX-3NF667C

• Family Name: 440GX
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.55/2.5V
• Operating Supply Voltage (max): 1.6/2.7V
• Operating Supply Voltage (min): 1.5/2.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 552
• Package Type: FCBGA
• Lead Free Status / Rohs Status: Compliant

Revision 1.20 – June 9, 2009
Signal Functional Description
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ to GND)
6. Strapping input during reset; pull-up (recommended value is 3kΩ to 3.3V) or pull-down (recommended value is 1kΩ to GND)
AMCC
System Interface
SysClk
SysErr
SysReset
TmrClk
Halt
GPIO00:31
TestEn
RcvrInh
RefVEn
DrvrInh2
Data Sheet
required
Signal Name
Main system clock input.
Set to 1 when a machine check is generated.
Main system reset. External logic can drive this bidirectional pin
low (minimum of 16 cycles) to initiate a system reset. A system
reset can also be initiated by software. The signal is implemented
as an open-drain output (two states; 0 or open circuit).
During chip power-up, this signal must be low from the start of V
ramp-up until at least 16 SysClk cycles after V
Processor timer external input clock.
Halt from external debugger.
General purpose I/O 0 through 10. To access these functions,
software must set DCR register bits.
Test Enable.
Receiver Inhibit. Active only when TestEn is active.
Reference Voltage Enable. Do not connect for normal operation.
Pull up for Boundary Scan Description Language (BSDL) testing.
Driver Inhibit. Used for test purposes only. Tie up for normal
operation
(Sheet 7 of 8)
Description
440GX – Power PC 440GX Embedded Processor
DD
is stable.
DD
Clock
I/O
I/O
I/O
O
I
I
I
I
I
I
3.3V tolerant
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
2.5V CMOS
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
w/pull-down
3.3V LVTTL
w/pull-up
Type
Notes
1, 2
1, 4
3
2
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