AT24C128C-SSHM-T Atmel, AT24C128C-SSHM-T Datasheet - Page 6

• Manufacturer Part Number: AT24C128C-SSHM-T
• Manufacturer: Atmel

Specifications of AT24C128C-SSHM-T

• Lead Free Status / Rohs Status: Compliant

4.
6
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may
change only during SCL low time periods (see
stop condition, as defined below.
Figure 4-1.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition that must precede any other
command (see
Figure 4-2.
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop
command will place the EEPROM in a standby power mode (see
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The
EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word.
STANDBY MODE: The Atmel AT24C128C features a low-power standby mode that is enabled upon power-up and after
the receipt of the stop bit and the completion of any internal operations.
SOFTWARE RESET: After an interruption in protocol, power loss, or system reset, any two-wire part can be protocol reset
by following these steps: (a) Create a start bit condition, (b) clock nine cycles, and (c) create another start bit followed by
stop bit condition, as shown below. The device is ready for the next communication after the above steps have been
completed.
SDA
SDA
SCL
Atmel AT24C128C
SCL
START
Data Validity
Start and Stop Definition
Figure
4-2).
DATA STABLE
CHANGE
DATA
Figure
DATA STABLE
4-1). Data changes during SCL high periods will indicate a start or
STOP
Figure
4-2).
8734A–SEEPR–1/11