AT24C128C-SSHM-T Atmel, AT24C128C-SSHM-T Datasheet - Page 3

• Manufacturer Part Number: AT24C128C-SSHM-T
• Manufacturer: Atmel

Specifications of AT24C128C-SSHM-T

• Lead Free Status / Rohs Status: Compliant

Atmel AT24C128C
2.
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and negative-edge
clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven, and may be wire-
ORed with any number of other open-drain or open-collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired
(directly to GND or to Vcc) for compatibility with other Atmel AT24Cxx devices. When the pins are hardwired, as many as
eight 128K devices may be addressed on a single bus system. (Device addressing is discussed in detail in
Section 5.
“Device Addressing” on page
8) A device is selected when a corresponding hardware and software match is true. If
these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive
coupling that may appear during customer applications, Atmel recommends always connecting the address pins to a

known state. When using a pull-up resistor, Atmel recommends using 10k
or less.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is
connected directly to Vcc, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be
internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel
recommends always connecting the WP pin to a known state. When using a pull-up resistor, Atmel recommends using

10k
or less.
3
8734A–SEEPR–1/11