AT24C128C-SSHM-T Atmel, AT24C128C-SSHM-T Datasheet - Page 10

• Manufacturer Part Number: AT24C128C-SSHM-T
• Manufacturer: Atmel

Specifications of AT24C128C-SSHM-T

• Lead Free Status / Rohs Status: Compliant

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Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the
current address data word is serially clocked out. The microcontroller does not respond with an input zero, but does
generate a following stop condition (see
Figure 7-1.
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the
device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must
generate another start condition. The microcontroller now initiates a current address read by sending a device address with
the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The
microcontroller does not respond with a zero, but does generate a following stop condition (see
Figure 7-2.
Note:
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the
microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge,
it will continue to increment the data word address and serially clock out sequential data words. When the memory
address limit is reached, the data word address will roll over and the sequential read will continue. The sequential read
operation is terminated when the microcontroller does not respond with a zero, but does generate a following stop
condition (see
Figure 7-3.
Atmel AT24C128C
*
= Don’t-carebit
Current Address Read
Random Read
Sequential Read
Figure
7-3).
Figure
7-1).
Figure
7-2).
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