NOIL1SM0300A-QDC ON Semiconductor, NOIL1SM0300A-QDC Datasheet - Page 5

• Manufacturer Part Number: NOIL1SM0300A-QDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SM0300A-QDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

image core consists of a pixel array, an X- and Y-addressing
register, pixel array drivers, and column amplifiers. The
image sensor of 640 x 480 pixels is read out in progressive
scan.
x-direction in steps of 8 pixels and in the y-direction in steps
of 1 pixel. The starting point of the address is uploadable by
means of the Serial Parallel Interface (SPI).
Pixel Architecture
The LUPA300 is designed on the 6T pixel architecture.
Color Filter
The LUPA300 can also be processed with a Bayer RGB
color pattern. Pixel (0,0) has a red filter.
The floor plan of the architecture is shown in Figure 4. The
The architecture allows programmable addressing in the
Figure 4. Floor Plan of the Sensor
SENSOR ARCHITECTURE
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offset so the signal fits in the input range of the ADC. The
four ADCs then convert the signal to the digital domain.
Pixels are selected in a 4 * 1 kernel. Every ADC samples the
signal from one of the 4 selected pixels. Sampling frequency
is 20 MHz. The digital outputs of the four ADCs are
multiplexed to one output bus operating at 80 MHz.
The PGAs amplify the signal from the column and add an
Figure 5. Color Filter Arrangement on the Pixels