NOIL1SM0300A-QDC ON Semiconductor, NOIL1SM0300A-QDC Datasheet - Page 10

• Manufacturer Part Number: NOIL1SM0300A-QDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SM0300A-QDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Biasing
this image sensor. For optimization reasons of the biasing of
1. Each biasing signal determines the operation of a corresponding module in the sense that it controls speed and dissipation.
Digital Signals
pixel array of the image sensor requires different digital
ADC_BIAS
PRECHARGE_BIAS
BIAS_PGA
BIAS_FAST
BIAS_SLOW
BIAS_COL
LINE_VALID
FRAME_VALID
INT_TIME_3
INT_TIME_2
INT_TIME_1
RESET_N
CLK
SPI_ENABLE
SPI_CLK
SPI_DATA
Table 9. OVERVIEW OF BIAS SIGNALS
Table 10. OVERVIEW OF BIAS SIGNALS
Table 9 summarizes the biasing signals required to drive
Depending on the operation mode (master or slave), the
Signal
Signal
[1]
Connect with 10 kW to V
Connect with 68 kW to V
GND
Biasing of amplifier stage. Connect with 110 kW to V
couple with 100 nF to GND
Biasing of columns. Connect with 42 kW to V
100 nF to GND
Biasing of columns. Connect with 1.5 MW to V
with 100 nF to GND
Biasing of imager core. Connect with 500 kW to V
with 100 nF to GND
Digital output
Digital output
Digital I/O
Digital I/O
Digital I/O
Digital input
Digital input
Digital input
Digital input
Digital I/O
DRIVERS
I/O
A
A
A
Indicates when valid data is at the outputs. Active high
Indicates when a valid frame is readout. Active high
In master mode: Output to indicate the triple slope integration time.
In slave mode: Input to control the triple slope integration time.
Active high
In master mode: Output to indicate the dual slope integration time.
In slave mode: Input to control the dual slope integration time.
Active high
In master mode: Output to indicate the integration time.
In slave mode: Input to control integration time.
Active high
Sequencer reset. Active low
Readout clock (80 MHz), sine or square clock
Enable of the SPI
Clock of the SPI. (Max. 20 MHz)
Data line of the SPI. Bidirectional pin
ADC
PIX
A
and decouple with 100 nF to
and decouple with 100n to GND
Comment
http://onsemi.com
10
DDA
the column amplifiers with respect to power dissipation,
several biasing resistors are required. This optimization
results in an increase of signal swing and dynamic range.
DDA
control signals. The function of each of the signals is shown
in Table 10.
and decouple with
DDA
and decouple
DDA
and decouple
and de-
Comments
ADC
Pixel array precharge
Column amplifiers
Column amplifiers
Column amplifiers
Related Module
ADC
PGA
DC−Level
693 mV
567 mV
650 mV
750 mV
450 mV
508 mV