NOIL1SM0300A-QDC ON Semiconductor, NOIL1SM0300A-QDC Datasheet - Page 15

• Manufacturer Part Number: NOIL1SM0300A-QDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SM0300A-QDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Voffset <7:0>
generates the Voffset supply used by the PGA. When the
register is ”00000000” it sets a Voffset of 2.5V. When the
register is 11111111 then it sets a Voffset of 0V. This means
that the minimum step you can take with the Voffset register
is 9.8 mV/bit (2.5V/256bits).
Ana_in_ADC <11:0>
ADC input (mainly for testing and debugging). The register
consists of several ”sub-registers”.
Sel_test_path (4 bits)
Sel_path (4 bits)
through test paths)
Bypass_mux (4 bits)
1 multiplexer.
PGA_SETTING <11:0>
register consists of different ”sub-registers”
Gain_pga (4 bits)
gives an overview of the different gain settings.
This register is the input for the on-chip DAC, which
This register sets the different paths that can be used as the
These bits select the analog test path of the ADC.
0000: No analog test path selected (default)
0001: Path of pixel 1 selected
0010: Path of pixel 2 selected
These bits select the analog path to the ADC.
1111: All paths selected (normal operation) - default
0000: No paths selected (enables ADC to be tested
0001: Path of pixel 1 selected
0010: Path of pixel 2 selected
These bits enable the possibility to bypass the digital 4 to
0000: no bypass (default)
This register defines all parameters to set the PGA. The
These bits set the gain of the PGA. The following Table 13
http://onsemi.com
15
Unity_pga (1 bit)
(default)
Sel_uni (1 bit)
amplification before the PGA.
Enable_analog_in (1 bit)
Enable_adc (4 bits)
ADCs.
Sel_calib_fast (1 bit)
Table 13.
This bit sets the PGA in unity amplification.
0: No unity amplification, gain settings apply
1: Unity gain amplification, gain setting are ignored
This bit selects whether or not the signal gets a 0.5
0: amplification of 0.5 before PGA
1: Unity feed through (default)
This bit enables/disables an analog input to the PGA.
0: analog input disabled (default)
1: analog input enabled
These bits can separately enable/disable the different
0000: No ADCs enabled
1111: All ADCs enabled (default)
0001: ADC 1 enabled
0010: ADC 2 enabled
Selects the fast/slow calibration of the ADC
0: slow calibration
1: fast calibration
GAIN_PGA<3.0>
0000
0001
0010
0100
0101
1000
1001
1010
0011
0110
0111
1011
1100
1101
1110
1111
13.12
15.38
Gain
1.32
1.56
1.85
2.18
2.58
3.05
3.59
4.22
5.84
6.84
8.02
9.38
11.2
4.9