NOIL1SM0300A-QDC ON Semiconductor, NOIL1SM0300A-QDC Datasheet - Page 22

• Manufacturer Part Number: NOIL1SM0300A-QDC
• Manufacturer: ON Semiconductor

Specifications of NOIL1SM0300A-QDC

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Startup Timing
other supplies. The rise of VDDD should be limited to
1V/100 ms to avoid activation of the on chip ESD protection
circuitry.
generated that resets the SPI registers to its default setting.
After VDDD is stable the SPI settings can be uploaded to
configure the sensor for future readout and light integration.
When powering on the VDDD supply, the RESET_N pin
System clock
Sequencer Reset Timing
sequencer is reset to its initial state. The internal clock
division is restarted. The second rising edge of CLK after the
VDDD power
RESET_N
Core clock
SPI upload
(external)
(internal)
(internal)
On startup, VDDD should rise together with or before the
During the rise of VDDD an on chip POR_N signal is
By bringing RESET_N low for at least 50 ns, the on chip
Core clock
(internal)
(internal)
(internal)
POR_N
RESET_N
(external)
supply
Clock_Y
System
Sync_Y
clock
POWER ON
INVALID
Normal operation
Min 500ns
SPI upload
Figure 24. Sequencer Reset Timing
Figure 23. Startup Timing
http://onsemi.com
Min 50 ns
22
INVALID
should be kept low to reset the on chip sequencer and
addressing logic. The RESET_N pin must remain low until
all initial SPI settings are uploaded. RESET_N pin must
remain low for at least 500 ns after ALL supplies are stable.
The rising edge of RESET_N starts the on chip clock
division. The second rising edge of CLK after the rising edge
of RESET_N, triggers the rising edge of the core clock.
Some SPI settings can be uploaded after the core clock has
started.
rising edge of RESET_N the internal clock is restarted. The
SPI settings are not affected by RESET_N. If needed the SPI
settings can be changed during a low level of RESET_N.
VDDD STABLE
INVALID
SPI upload if required
Normal operation