ADC104S021EVAL National Semiconductor, ADC104S021EVAL Datasheet - Page 7

• Manufacturer Part Number: ADC104S021EVAL
• Manufacturer: National Semiconductor

Specifications of ADC104S021EVAL

• Lead Free Status / Rohs Status: Not Compliant

Specification Definitions
ACQUISITION TIME is the time required to acquire the input
voltage. That is, it is time required for the hold capacitor to
charge up to the input voltage.
APERTURE DELAY is the time between the fourth falling
SCLK edge of a conversion and the time when the input signal
is acquired or held for conversion.
CONVERSION TIME is the time required, after the input volt-
age is acquired, for the ADC to convert the input voltage to a
digital word.
CROSSTALK is the coupling of energy from one channel into
the other channel, or the amount of signal energy from one
analog input that appears at the measured analog input.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
DUTY CYCLE is the ratio of the time that a repetitive digital
waveform is high to the total time of one period. The specifi-
cation here refers to the SCLK.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion
(SINAD − 1.76) / 6.02 and says that the converter is equiva-
lent to a perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
FULL SCALE ERROR (FSE) is a measure of how far the last
code transition is from the ideal 1½ LSB below V
defined as:
where V
mum code occurs. FSE can be expressed in Volts, LSB or
percent of full scale range.
GAIN ERROR is the deviation of the last code transition
(111...110) to (111...111) from the ideal (V
ter adjusting for offset error.
INTEGRAL NON-LINEARITY (INL) is a measure of the de-
viation of each individual code from a line drawn from negative
full scale (½ LSB below the first code transition) through pos-
itive full scale (½ LSB above the last code transition). The
deviation of any given code from this straight line is measured
from the center of that code value.
max
is the voltage at which the transition to the maxi-
or
V
FSE
SINAD.
= V
max
+ 1.5 LSB – V
ENOB
is
REF
REF
+
− 1.5 LSB), af-
defined
REF
+
and is
as
7
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the second and third
order intermodulation products to the power in one of the
original frequencies. IMD is usually expressed in dB.
MISSING CODES are those output codes that will never ap-
pear at the ADC outputs. These codes cannot be reached with
any input value. The ADC104S021 is guaranteed not to have
any missing codes.
OFFSET ERROR is the deviation of the first code transition
(000...000) to (000...001) from the ideal (i.e. GND + 0.5 LSB).
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the sam-
pling frequency, not including harmonics or d.c.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or
SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral com-
ponents below half the clock frequency, including harmonics
but excluding d.c.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal and the peak spurious signal where a spurious signal
is any signal present in the output spectrum that is not present
at the input, excluding d.c.
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB or dBc, of the rms total of the first five harmonic
components at the output to the rms level of the input signal
frequency as seen at the output. THD is calculated as
where A
put and A
harmonic frequencies.
THROUGHPUT TIME is the minimum time required between
the start of two successive conversion. It is the acquisition
time plus the conversion and read out times. In the case of
the ADC104S021, this is 16 SCLK periods.
f1
is the RMS power of the input frequency at the out-
f2
through A
f6
are the RMS power in the first 5
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