ADC104S021EVAL National Semiconductor, ADC104S021EVAL Datasheet - Page 16

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ADC104S021EVAL

Manufacturer Part Number
ADC104S021EVAL
Description
Manufacturer
National Semiconductor
Datasheet

Specifications of ADC104S021EVAL

Lead Free Status / Rohs Status
Not Compliant
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During each conversion, data is clocked into the DIN pin on
the first 8 rising edges of SCLK after the fall of CS. For each
conversion, it is necessary to clock in the data indicating the
input that is selected for the conversion after the current one.
See Tables 1, 2 and Table 3.
If CS and SCLK go low within the times defined by t
t
DIN may be one clock cycle later than expected. It is, there-
3.0 ADC104S021 TRANSFER FUNCTION
The output format of the ADC104S021 is straight binary.
Code transitions occur midway between successive integer
LSB values. The LSB width for the ADC104S021 is V
The ideal transfer characteristic is shown in Figure 3. The
CLH
, the rising edge of SCLK that begins clocking data in at
Bit 7 (MSB)
DONTC
Bit #:
7 - 6, 2 - 0
5
4
3
Symbol:
DONTC
Bit 6
DONTC
ADD2
ADD1
ADD0
ADD2
TABLE 2. Control Register Bit Descriptions
Description
Don't care. The value of these bits do not affect device operation.
These three bits determine which input channel will be sampled and converted
in the next track/hold cycle. The mapping between codes and channels is shown
in Table 3.
x
x
x
x
ADD2
FIGURE 3. Ideal Transfer Characteristic
Bit 5
TABLE 3. Input Channel Selection
TABLE 1. Control Register Bits
ADD1
CSU
A
0
0
1
1
/1024.
ADD1
and
Bit 4
16
ADD0
0
1
0
1
fore, best to strictly observe the minimum t
given in the Timing Specifications.
There are no power-up delays or dummy conversions re-
quired with the ADC104S021. The ADC is able to sample and
convert an input to full conversion immediately following pow-
er up. The first conversion result after power-up will be that of
IN1.
transition from an output code of 00 0000 0000 to a code of
00 0000 0001 is at 1/2 LSB, or a voltage of V
code transitions occur at steps of one LSB.
ADD0
Bit 3
Input Channel
IN1 (Default)
IN2
IN3
IN4
DONTC
Bit 2
20124411
DONTC
Bit 1
CSU
and t
A
/2048. Other
DONTC
Bit 0
CLH
times