IPR-CSC Altera, IPR-CSC Datasheet - Page 26

• Manufacturer Part Number: IPR-CSC
• Description: IP COLOR SPACE CONVERTER RENEW
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-CSC

• Function: Color Space Converter
• License: Renewal License
• Lead Free Status / Rohs Status: Not applicable / Not applicable

Simulate the Design
Simulate the
Design
Compile the
Design
Program a
Device
2–16
Color Space Converter MegaCore Function User Guide
Notes to
(1)
<variation name>.vhd, or .v
<variation name>_bb.v
Table 2–1. IP Toolbench-Generated Files (Part 2 of 2)
<variation name> is the variation name.
Table
2–1:
f
f
Filename
You can now integrate your CSC MegaCore function variation into your
design and simulate and compile.
You can simulate your design using the IP Toolbench-generated VHDL
and Verilog HDL IP functional simulation models. The IP functional
simulation model is the .vo or .vho file you specified in
Simulation” on page
environment and perform functional simulation of your custom CSC
MegaCore function.
For more information on IP functional simulation models, refer to the
Simulating Altera in Third-Party Simulation Tools chapter in volume 3 of
the Quartus II Handbook.
You can use the Quartus II software to compile your design. Refer to
Quartus II Help for instructions on performing compilation.
Refer to Quartus II Help (F1) or the Introduction to Quartus II Handbook
for further instructions on compiling and analyzing your design.
After you have compiled your design, program your targeted Altera
device, and verify your design in hardware.
With Altera's free OpenCore Plus evaluation feature, you can evaluate the
CSC MegaCore function before you purchase a license. OpenCore Plus
evaluation allows you to generate an IP functional simulation model, and
produce a time-limited programming file.
MegaCore Version 2.3.0
A MegaCore function variation file, which defines a VHDL
or Verilog HDL top-level description of the custom
MegaCore function. Instantiate the entity defined by this
file inside of your design. Include this file when compiling
your design in the Quartus II software.
Verilog HDL black-box file for the MegaCore function
variation. Use this file when using a third-party EDA tool to
synthesize your design.
2–12. Compile the file in your simulation
Note (1)
Description
Altera Corporation
“Step 2: Set Up
October 2005