3342-5 Peregrine Semiconductor, 3342-5 Datasheet - Page 2

• Manufacturer Part Number: 3342-5
• Description: EVAL KIT FOR PE3342
• Manufacturer: Peregrine Semiconductor
• Series: -r

Specifications of 3342-5

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 3342-05; 3342-50

Figure 2. Pin Configuration (Top View)
Table 2. Pin Descriptions
Notes 1: V
©2005-8 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 17
Pin No.
S_WR
E_WR
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
Clock
FSel
2: Ground connections are made through the exposed solder pad. The solder pad must be soldered to the ground plane for proper operation.
Data
DD
1
2
3
4
5
pins 7, 14 and 19 are connected by diodes and must be supplied with the same positive voltage level.
Pin Name
S_WR
Data
Clock
FSel
E_WR
V
V
F
F
C
EELoad
LD
Dout
V
PD_D
PD_U
EESel
f
V
ENH
r
PP
DD
in
in
DD
DD
EXT
20-lead QFN
Exposed Solder Pad
(Bottom Side)
4x4mm
Input
Input
Input
Input
Input
Input
(Note 1)
Input
Input
Output
Input
Output, OD
Output
(Note 1)
Output
Output
Input
Input
(Note 1)
Input
Type
15
14
13
12
11
PD_D
V
Dout
LD
EELoad
DD
Secondary Register WRITE input. Primary Register contents are copied to the Secondary Register on
S_WR rising edge. Also used to control Serial Port operation and EEPROM programming.
Binary serial data input. Input data entered LSB (B
Serial clock input. Data is clocked serially into the 20-bit Primary Register, the 20-bit EE Register, or
the 8-bit Enhancement Register on the rising edge of Clock. Also used to clock EE Register data out
Dout port.
Frequency Register selection control line. Internal 70 kW pull-down resistor.
Enhancement Register write enable. Also functions as a Serial Port control line. Internal 70 kW pull-
down resistor.
EEPROM erase/write programming voltage supply pin. Requires a 100pF bypass capacitor connected
to GND.
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.
Prescaler input from the VCO.
Prescaler complementary input. A series 50 W resistor and DC blocking capacitor should be placed as
close as possible to this pin and connected to the ground plane.
Logical “NAND” of PD_U and PD_D terminated through an on-chip, 2 kW series resistor. Connecting
C
Control line for Serial Data Port, Frequency Register selection, EE Register parallel loading, and
EEPROM programming. Internal 70 kW pull-down resistor.
Lock detect output, an open-drain logical inversion of C
impedance; otherwise, LD is a logic LOW.
Data out function. Dout is defined with the Enhancement Register and enabled with ENH.
Same as pin 7.
Phase detector output. PD_D pulses negatively when fp leads fc.
Phase detector output. PD_U pulses negatively when fc leads fp.
Control line for Frequency Register selection, EE Register parallel loading, and EEPROM
programming. Internal 70 kW pull-up resistor.
Reference frequency input.
Same as pin 7.
Enhancement mode control line. When asserted LOW, enhancement register bits are functional.
Internal 70 kW pull-up resistor.
EXT
to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD.
Figure 3. Package Type
20-lead QFN
Document No. 70-0091-04 │ UltraCMOS™ RFIC Solutions
Description
0
) first.
EXT
. When the loop is in lock, LD is high
Product Specification
PE3342