EA-XPR-007 Embedded Artists, EA-XPR-007 Datasheet - Page 28

• Manufacturer Part Number: EA-XPR-007
• Description: BOARD LPCXPRESSO LPC11U14
• Manufacturer: Embedded Artists

Specifications of EA-XPR-007

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC11U1X
Objective data sheet
CAUTION
7.13.6.4 APB interface
7.13.6.5 AHBLite
7.13.6.6 External interrupt inputs
7.14 Emulation and debugging
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details see the LPC11U1x user manual.
The APB peripherals are located on one APB bus.
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the ROM.
All GPIO pins can be level or edge sensitive interrupt inputs.
Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are
supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is
configured to support up to four breakpoints and two watch points.
The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM
SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the
LPC11U1x is in reset.
Remark: Boundary scan operations should not be started until 250 s after POR, and the
test TAP should be reset after the boundary scan. Boundary scan is not affected by Code
Read Protection.
1. CRP1 disables access to the chip via the SWD and allows partial flash update
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
3. Running an application with level CRP3 selected fully disables any access to the chip
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors can
not be erased.
update using a reduced set of the ISP commands.
via the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
the USART.
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 11 April 2011
32-bit ARM Cortex-M0 microcontroller
LPC11U1x
© NXP B.V. 2011. All rights reserved.
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