EA-XPR-005 Embedded Artists, EA-XPR-005 Datasheet
EA-XPR-005
Specifications of EA-XPR-005
Related parts for EA-XPR-005
EA-XPR-005 Summary of contents
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... The peripheral complement of the LPC122x includes a 10-bit ADC, two comparators with output feedback loop, two UARTs, one SSP/SPI interface, one I Fast-mode Plus features, a Windowed Watchdog Timer, a DMA controller, a CRC engine, four general purpose timers, a 32-bit RTC internal oscillator for baud rate generation, and General Purpose I/O (GPIO) pins ...
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... Clock output function with divider that can reflect the system oscillator clock, IRC clock, main clock, and Watchdog clock. Real-Time Clock (RTC). LPC122X Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 29 March 2011 ...
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... Processor wake-up from Deep-sleep mode via start logic using 12 port pins. Processor wake-up from Deep-power down and Deep-sleep modes via the RTC. Brownout detect with three separate thresholds each for interrupt and forced reset. Power-On Reset (POR). ...
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... LPC1225FBD64/301 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2 LPC1224FBD64/121 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2 LPC1224FBD64/101 LQFP64 LQFP64: plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2 LPC1227FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package ...
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NXP Semiconductors 5. Block diagram LPC122x TEST/DEBUG CORTEX-M0 HIGH-SPEED GPIO ports SCK SSEL MISO MOSI RXD0 TXD0 UART0 RS-485 DTR0, DSR0, CTS0, DCD0, RI0, RTS0 RXD1 TXD1 SCL SDA 4 × MAT 32-bit COUNTER/TIMER 0 4 × CAP 4 × ...
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... Pinning XTALIN XTALOUT VREF_CMP PIO0_19 PIO0_20 PIO0_21 PIO0_22 PIO0_23 PIO0_24 SWDIO/PIO0_25 SWCLK/PIO0_26 (1) PIO0_27 PIO2_12 PIO2_13 PIO2_14 PIO2_15 (1) High-current output driver. Remark: For a full listing of all functions for each pin see Fig 2. Pin configuration LQFP64 package LPC122X Objective data sheet LPC122x ...
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... NXP Semiconductors XTALIN XTALOUT VREF_CMP PIO0_19 PIO0_20 PIO0_21 PIO0_22 PIO0_23 PIO0_24 SWDIO/PIO0_25 SWCLK/PIO0_26 PIO0_27 (1) High-current output driver. Remark: For a full listing of all functions for each pin see Fig 3. Pin configuration LQFP48 package LPC122X Objective data sheet LPC122x (1) 12 Table 3. All information provided in this document is subject to legal disclaimers. ...
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... IOCON register in the IOCONFIG block. The multiplexed functions (see UART receive, transmit, and control functions, and the serial wire debug functions. For each pin, the default function is listed first together with the pin’s reset state. Table 3. LPC122x pin description ...
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... I PIO0_7 — General purpose digital input/output pin CTS0 — Clear To Send input for UART0 CT32B1_CAP1 — Capture input, channel 1 for 32-bit timer CT32B1_MAT1 — Match output, channel 1 for 32-bit timer 1. [2] yes I PIO0_8 — General purpose digital input/output pin. ...
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NXP Semiconductors Table 3. LPC122x pin description Symbol PIO0_17/MOSI 32 44 PIO0_18/SWCLK CT32B0_CAP0/ CT32B0_MAT0 PIO0_19/ACMP0_I0 CT32B0_CAP1/ CT32B0_MAT1 PIO0_20/ACMP0_I1 CT32B0_CAP2/ CT32B0_MAT2 PIO0_21/ACMP0_I2 CT32B0_CAP3/ CT32B0_MAT3 PIO0_22/ACMP0_I3 7 7 PIO0_23 ACMP1_I0/ CT32B1_CAP0/ CT32B1_MAT0 ...
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... AD1 — A/D converter, input 1. I/O Port 1 — Port 32-bit I/O port with individual direction and function controls for each bit. The operation of port 1 pins depends on the function selected through the IOCONFIG register block. Pins PIO1_7 through PIO1_31 are not available. ...
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... CT16B1_MAT1 — Match output, channel 1 for 16-bit timer 1. I/O Port 2 — Port 32-bit I/O port with individual direction and function controls for each bit. The operation of port 2 pins depends on the function selected through the IOCONFIG register block. Pins PIO2_16 through PIO2_31 are not available ...
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... PIO2_7 — General purpose digital input/output pin CT32B0_CAP3 — Capture input, channel 3 for 32-bit timer CT32B0_MAT3 — Match output, channel 3 for 32-bit timer DSR0 — Data Set Ready input for UART0. [ PIO2_8 — General purpose digital input/output pin CT32B1_CAP0 — Capture input, channel 0 for 32-bit timer 1. ...
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NXP Semiconductors Table 3. LPC122x pin description Symbol DD(IO DD(3V3 SSIO [1] Pin state at reset for default function Input Output ...
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NXP Semiconductors Table 4. Peripheral CT16B0 CT16B1 CT32B0 CT32B1 UART0 UART1 SSP/SPI I2C LPC122X Objective data sheet Pin multiplexing Function CT16B0_CAP0 CT16B0_CAP1 CT16B0_MAT0 CT16B0_MAT1 CT16B1_CAP0 CT16B1_CAP1 CT16B1_MAT0 CT16B1_MAT1 CT32B0_CAP0 CT32B0_CAP1 CT32B0_CAP2 CT32B0_CAP3 CT32B0_MAT0 CT32B0_MAT1 CT32B0_MAT2 CT32B0_MAT3 CT32B1_CAP0 CT32B1_CAP1 CT32B1_CAP2 CT32B1_CAP3 ...
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... The interrupt vector area supports address remapping. The AHB peripheral area is 2 megabyte in size, and is divided to allow for up to 128 peripherals. The APB peripheral area is 512 kB in size and is divided to allow for peripherals. Each peripheral of either type is allocated 16 kilobytes of space. This allows simplifying the address decoding for each peripheral ...
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... Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC integral part of the Cortex-M0. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 7.5.1 Features • Controls system exceptions and peripheral interrupts. LPC122X ...
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... Non-maskable Interrupt (NMI) can be programmed to use any of the peripheral interrupts. The NMI is not available on an external pin. 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. ...
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... The value of the output register may be read back as well as the current state of the port pins. 7.9.1 Features • Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. • Direction control of individual bits. ...
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... The I C-bus is bidirectional for inter-IC control using only two wires: a serial clock line (SCL) and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed ...
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... Burst conversion mode for single or multiple inputs. • Optional conversion on transition of input pin or counter/timer match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. 7.14 Comparator block The comparator block consists of two analog comparators. 7.14.1 Features • ...
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... The timer and prescaler may be configured to be cleared on a designated capture event. This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge. • Supports timed DMA requests. ...
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... The LPC122x include four independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), the RTC 32 kHz oscillator (for the RTC only), and the Watchdog oscillator. Except for the RTC oscillator, each oscillator can be used for more than one purpose as required in a particular application. ...
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NXP Semiconductors IRC oscillator watchdog oscillator MAINCLKSEL (main clock select) IRC oscillator SYSTEM PLL system oscillator SYSPLLCLKSEL Fig 5. LPC122x clocking generation block diagram 7.18.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, ...
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... MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. ...
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... Deep power-down mode. 7.19 System control 7.19.1 Start logic The start logic connects external pins to corresponding interrupts in the NVIC. Each pin shown in vector table. The start logic pins can serve as external interrupt pins when the chip is running. In addition, an input signal on the start logic pins can wake up the chip from Deep-sleep mode when all clocks are shut down ...
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... BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. An additional threshold level can be selected to cause a forced reset of the chip ...
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NXP Semiconductors 7.20 Emulation and debugging Debug functions are integrated into the ARM Cortex-M0. Serial wire debug is supported. 7.21 Integer division routines The LPC122x contain performance-optimized integer division routines with support for up to 32-bit width in the numerator ...
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... The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V otherwise noted ...
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NXP Semiconductors 9. Thermal characteristics 9.1 Thermal characteristics The average chip junction temperature, T equation amb • T amb • R th(j-a) • The internal power dissipation is the product of I the I/O ...
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NXP Semiconductors 10. Static characteristics Table 7. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter V input/output supply DD(IO) voltage V supply voltage (3.3 V) DD(3V3) I supply current DD ...
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... C-bus pins (PIO0_10 and PIO0_11) V HIGH-level input IH voltage V LOW-level input IL voltage V hysteresis voltage hys V LOW-level output OL voltage I input leakage current LI C capacitance for each i I/O pin LPC122X Objective data sheet …continued Conditions = 2 Normal-drive pins; low mode Normal-drive pins; high mode High-drive pins ...
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NXP Semiconductors Table 7. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter Oscillator pins V crystal input voltage i(xtal) V crystal output voltage o(xtal) Typical ratings are not guaranteed. The ...
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... NXP Semiconductors 10.1 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at T noted otherwise, the system oscillator and PLL are running in both measurements. The supply currents are shown for system clock frequencies of < ...
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NXP Semiconductors (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 6. (mA) Fig 7. LPC122X Objective data sheet <tbd> ...
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NXP Semiconductors (mA) Fig 8. (1) System oscillator and system PLL disabled; IRC enabled. (2) System oscillator and system PLL enabled; IRC disabled. Fig 9. LPC122X Objective data sheet −40 −15 Conditions: V ...
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NXP Semiconductors (μA) Fig 10. Deep-sleep mode: Typical supply current I Fig 11. Deep power-down mode: Typical supply current I LPC122X Objective data sheet 3.6 V DD(3V3) 3 ...
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NXP Semiconductors 10.3 Electrical pin characteristics Fig 12. High-drive output: Typical HIGH-level output voltage V Fig 13. I LPC122X Objective data sheet <tbd> Conditions 3.3 V. DD(IO) output ...
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NXP Semiconductors Fig 14. Typical LOW-level output current I Fig 15. Typical HIGH-level output voltage V LPC122X Objective data sheet <tbd> Conditions 3.3 V. DD(IO (X) ...
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NXP Semiconductors Fig 16. Typical pull-up current I LPC122X Objective data sheet <tbd> Conditions 3.3 V. DD(IO) versus input voltage V pu All information provided in this document ...
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... The offset error (E straight line which fits the ideal curve. See [7] The gain error (E curve after removing offset error, and the straight line which fits the ideal transfer curve. See [8] The absolute error (E curve of the non-calibrated ADC and the ideal transfer curve. See ...
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... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 17. ADC characteristics LPC122X Objective data sheet (2) (5) (4) (3) 1 LSB (ideal (LSB ...
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NXP Semiconductors 10.5 BOD static characteristics Table 10 amb Symbol V th [1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see LPC122x user manual. LPC122X Objective data sheet [1] ...
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... Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages. Fig 18. External clock timing (with an amplitude of at least V LPC122X Objective data sheet Dynamic characteristic: flash memory ...
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... Fig 19. Internal RC oscillator frequency versus temperature Table 14. Symbol Parameter f osc(int) Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [1] voltages. [2] The typical frequency spread over processing and temperature (T [3] See the LPC122x user manual. 2 11.4 I C-bus Table 15. Dynamic characteristic: I ...
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... This maximum must only be met if the device does not stretch the LOW period (t VD;ACK the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [8] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge. 2 [9] ...
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NXP Semiconductors SDA SCL SCL 2 Fig 20. I C-bus pins clock timing LPC122X Objective data sheet t SU;DAT ...
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NXP Semiconductors 11.5 SSP/SPI interface Table 16. Dynamic characteristics: SSP pins in SPI mode amb Symbol Parameter T clock cycle time cy(clk) SSP master t data set-up time DS t data hold time DH t ...
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NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 21. SSP master timing in SPI mode LPC122X Objective data sheet T cy(clk) t v(Q) DATA VALID MOSI MISO DATA VALID t v(Q) DATA VALID MOSI t DATA VALID ...
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NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 22. SSP slave timing in SPI mode LPC122X Objective data sheet T cy(clk) MOSI DATA VALID t v(Q) MISO DATA VALID t MOSI DATA VALID t v(Q) MISO DATA ...
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... Loops must be made as small as possible in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of C accordingly to the increase in parasitics of the PCB layout. LPC122X Objective data sheet which attenuates the input voltage by a factor C ...
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... NXP Semiconductors 12.3 ElectroMagnetic Compatibility (EMC) Radiated emission measurements according to the IEC61967-2 standard using the TEM-cell method are shown for the LPC1227FBD64/301 in Table 17 3 Parameter Input clock: IRC (12 MHz) maximum peak level IEC level Input clock: crystal oscillator (12 MHz) maximum peak level ...
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... NXP Semiconductors 13. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT313-2 136E05 Fig 25 ...
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NXP Semiconductors 14. Abbreviations Table 18. Acronym ADC AHB APB BOD CCITT CRC DMA FIFO GPIO I/O IrDA IRC JEDEC PLL SPI SSI SSP UART LPC122X Objective data sheet Abbreviations Description Analog-to-Digital-Converter Advanced High-performance Bus Advanced Peripheral Bus BrownOut Detection ...
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... RTCXOUT changed to 57. Objective data sheet • Section 1 “General description”: Updated text. • Section 2 “Features and benefits”: Updated text. Objective data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.2 — 29 March 2011 LPC122x 32-bit ARM Cortex-M0 microcontroller ...
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... NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’ ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s 17. Contact information For more information, please visit: For sales office addresses, please send an email to: LPC122X Objective data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2 7.12 I C-bus serial I/O controller . . . . . . . . . . . . . . 20 7.12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.13 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.14 Comparator block . . . . . . . . . . . . . . . . . . . . . . 21 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.15 General purpose external event counter/timers . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.16 Windowed WatchDog timer (WWDT 7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.17 Real-time clock (RTC 7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.18 Clocking and power control ...
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... Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 32-bit ARM Cortex-M0 microcontroller Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com LPC122x All rights reserved ...