HSDC-JAKIT1W2/DB NXP Semiconductors, HSDC-JAKIT1W2/DB Datasheet - Page 2

• Manufacturer Part Number: HSDC-JAKIT1W2/DB
• Description: DAC/ADC LATTICE KIT
• Manufacturer: NXP Semiconductors
• Series: -r

Specifications of HSDC-JAKIT1W2/DB

• Main Purpose: Interface, ADC/DAC for Lattice ECP3 FPGA
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: ADC1413D, DAC1408D, ECP3 FPGA
• Primary Attributes: Loop Back Demo with 2 High Speed Converters
• Secondary Attributes: USB Powered
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-6898

interface standard, with enhanced rate (4.0 Gbps typical),
enhanced reach (100 cm typical), enhanced features (multiple
DAC synchronization) and assured FPGA interoperability.
Specifically, NXP offers enhancements in terms of transceiver
rate (up to 4.0 Gbps versus the standard rate of 3.125 Gbps,
a 28% increase) and transmitter reach (up to 100 cm versus
the standard reach of 20 cm, a 400% increase). The enhanced
CGV features include Multi Device Synchronization (MDS),
which is not specified, but informatively discussed in the
JEDEC specification. NXP has implemented this optional
feature to enable LTE MIMO base station and other advanced
multichannel applications. NXP’s implementation of MDS
enables several DACs data streams to be sample synchronized
and phase coherent.
DAC1408D750 block diagram
DAC1x08D selection table
650Msps maximum output rate is also available for DAC1408D, DAC1208D and DAC1008D
Demo boards are also available for all resolutions (10, 12 and 14-bit) and all speeds (650 and 750 Msps)
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Family
DAC1408D series
DAC1208D series
DAC1008D series
Type
DAC1408D series
DAC1408D750
DAC1208D750
DAC1008D750
Type
Dual 14-bit DAC 750 Msps
Dual 12-bit DAC 750 Msps
Dual 10-bit DAC 750 Msps
Description
Related demoboard
DAC1408D650W0/DB
DAC1408D650W1/DB
DAC1408D750W0/DB
DAC1408D750W1/DB
LVCMOS
CGV
•
•
•
TM
This new interface has numerous advantages over the traditional
parallel one: easy PCB layout, lower pin count, reduced PCB
layers and cost, lower radiated noise, self-synchronous link,
skew compensation.
Other features include a two’s complement or binary-offset data
format, and 76 dBc IMD3 at F
DAC1408D series also include an LVDS compatible clock with
multiplier capable of x2, x4 and x8 operation and internal
regulation to adjust the output full scale current up to 20 mA.
A digital offset correction can be used to adjust the common
mode level at the DAC output. And 2 embedded auxiliary DACs
-current mode sources allow offset compensation between the
DAC and the next stage in your transmission path.
voltage (V)
Supply
1.8 / 3.3
1.8 / 3.3
1.8 / 3.3
Date of release: August 2010
Document order number : 9397 750 16888
Printed in the Netherlands
Dissipation per
channel (mW)
Power
700
700
700
Description
DAC1408D650 demo board
DAC1408D650 demo board with Virtex 5 FPGA
DAC1408D750 demo board
DAC1408D750 demo board with Virtex 5 FPGA
DAC
SFDR
(dBc)
77
77
77
Example of reference design
with DAC1408D750 and FPGA
DAC1408D750 demonstration
board, for easy connection to
Altera, Xilinx or Lattice
evaluation kit
= 640 Msps and F
www.nxp.com/dataconverters
Interpolation
2x, 4x, 8x
2x, 4x, 8x
2x, 4x, 8x
OUT
HVQFN64 9x9
HVQFN64 9x9
HVQFN64 9x9
= 140 MHz.
Package