HD64570F16 Renesas Electronics America, HD64570F16 Datasheet - Page 87

• Manufacturer Part Number: HD64570F16
• Description: IC SCA SRL COMM ADAPTER 88QFP
• Manufacturer: Renesas Electronics America

Specifications of HD64570F16

• Applications: ISDN
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 88-QFP
• Mounting Type: Surface Mount
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.4.2
In slave mode, data moves from the SCA to MPU in a read cycle, and from MPU to the SCA in a
write cycle. The address and bus interface signals are input signals, except for WAIT, which is an
output signal.
CPU Mode 0: The SCA latches BHE and the address on lines A0 to A7 when CS is driven active
low. CS must remain low throughout the bus cycle. After the bus cycle ends, CS may be either
high or low. CS may also be low before the beginning of the bus cycle. Figure 3.9 shows the slave
mode bus timing sequence in CPU mode 0.
Read cycle
If RD is low (active) at the falling clock edge between the T
the contents of the register specified by the address on the data bus on the rising clock edge in
the T
(inactive), the cycle ends: the SCA then drives the WAIT output active high and lets the data
bus float. The read cycle can be extended by delaying the high transition of RD.
Write cycle
If WR is low (active) at the falling clock edge between the T
the data on the data bus on the rising clock edge in the T
register specified by the address. WR must remain low until the rising clock edge in the T
state. When WR goes high (inactive), the cycle ends: the SCA then drives the WAIT output
active high.
When successive slave mode bus cycles or interrupt acknowledge cycles occur in CPU mode
0, at least one T
when the next cycle is not a slave mode bus cycle or an interrupt acknowledge cycle.
Figure 3.8 Data Bus Mapping onto Memory Banks in CPU Modes 0, 2, and 3
Odd-address
E
memory bank
3
BHE
Slave Mode Bus Cycle
state. RD must remain low until the beginning of the T
D
15
D
to D
15
i
to D
state (idle state) must be inserted between cycles. No T
8
MPU
8
D to D
7
memory bank
Even-address
D to D
7
0
A
0
0
E
Even-address
E
memory bank
HDS
3
state, and stores the data in the
D
15
1
1
and T
4
D
and T
to D
state. When RD goes high
15
Rev. 0, 07/98, page 71 of 453
to D
8
2
2
states, the SCA outputs
states, the SCA latches
MPU
8
D to D
i
state is necessary
7
memory bank
Odd-address
D to D
7
0
LDS
0
E
4