HD64570F16 Renesas Electronics America, HD64570F16 Datasheet - Page 145

• Manufacturer Part Number: HD64570F16
• Description: IC SCA SRL COMM ADAPTER 88QFP
• Manufacturer: Renesas Electronics America

Specifications of HD64570F16

• Applications: ISDN
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 88-QFP
• Mounting Type: Surface Mount
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -20C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 5.2
Command Name
(Set Value)
RX enable (12H)
RX disable (13H)
RX CRC initialization
(14H)
Message reject (15H) Allows the receiver to re-establish character synchronization in byte
Search MP bit (16H)
RX CRC calculation
exclusion (17H)
Receive Commands (cont)
Function
Sets the receiver to start bit search state in asynchronous mode, SYN1
wait state in byte synchronous mode, and flag wait state in bit
synchronous mode.
When the receiver is in enable state, this command is invalid.
For auto-enable operation , see the description of the AUTO bit in section
5.2.1, MSCI Mode Register 0 (MD0).
Halts the receive shift register and sets the receiver to RX disable state
while deleting the receive shift register contents, but without affecting the
receive buffer contents.
Initializes the receiver CRC calculator, as specified by the CRC0 bit of
MD0, when the first receive character is transferred to the receive shift
register after this command is issued.
This command is used in byte or bit synchronous mode
synchronous mode.
Prevents transfer of the current data frame to the receive buffer in bit
synchronous mode. Data transfer to the receive buffer resumes in the next
frame. In bit synchronous mode, the message reject command must be
issued only during character reception, or must be immediately followed by
a receive buffer clear command. Otherwise, the frame currently being
received may not be received correctly.
Prevents receive characters with MP bit = 0 from being loaded into the
receive buffer. This command remains valid until a character with MP bit =
1 is received. If necessary, re-issue this command after receiving a
character with MP bit = 1. For details, see Multiprocessor Support, in
section 5.3.1.
This command is valid only in asynchronous mode.
Excludes one specific character from the receiver CRC calculation.
This command must be issued within 8 bit cycles after the character that
will be excluded from the CRC calculation is input to the receive buffer.
This command operation is not guaranteed in modes other than byte
synchronous mode.
Rev. 0, 07/98, page 129 of 453