HD64570F16 Renesas Electronics America, HD64570F16 Datasheet - Page 302
HD64570F16
Manufacturer Part Number
HD64570F16
Description
IC SCA SRL COMM ADAPTER 88QFP
Manufacturer
Renesas Electronics America
Datasheet
1.HD64570F16.pdf
(469 pages)
Specifications of HD64570F16
Applications
ISDN
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Package / Case
88-QFP
Mounting Type
Surface Mount
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temp Range
-20C to 75C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Price
Company:
Part Number:
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Manufacturer:
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Quantity:
10 000
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HD64570F16
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HD64570F16V
Manufacturer:
INFINEON
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The operation flow in MSCI-to-memory chained-block transfer mode is shown in figure 6.19. As
shown in the figure, the DMAC transfers data from the MSCI receiver to the buffer corresponding
to the descriptor specified by CPB and CDA. At this time, the DMAC writes the 24-bit memory
address of the buffer currently being written to the buffer address register (BAR) and the number
of bytes remaining unwritten in the buffer to the byte count register (BCR). When data transfer
starts, the DMAC writes the BP value of the corresponding descriptor to BAR and the BFL value
to BCR.
The BAR value is incremented by 1 or 2 each time one byte or one word of data is transferred,
respectively. Similarly, the BCR value is decremented by 1 or 2 each time one byte or one word
of data is transferred, respectively. When the BCR value reaches 0000H, the DMAC terminates
data transfer, writes the receive data length to the descriptor, and updates the CDA value to
indicate the start address of the next descriptor (buffer switching). The DMAC, at that time,
Rev. 0, 07/98, page 286 of 453
CPB:
EDA:
CDA:
BAR:
BCR:
BFL:
EDA (16 bits)
CDA (16 bits)
BAR (24 bits)
BCR (16 bits)
BFL (16 bits)
CPB (8 bits)
HD64570
Chain pointer base
Error descriptor address register
Current descriptor address register
Buffer address register
Byte count register
Receive buffer length
Figure 6.18 MSCI-to-Memory Chained-Block Transfer
High-order 8 bits of the
descriptor address
Start address of the
write overflow descriptor
(low-order 16 bits)
Start address of the
descriptor being written
(low-order 16 bits)
Memory address of
the data being written
Byte count of the data
remaining in the buffer
being written
Receive buffer length
(byte count)
System memory
Descriptor
: Empty buffer
: Receive data
Current write position
Buffer
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