DP83266VF National Semiconductor, DP83266VF Datasheet - Page 93

• Manufacturer Part Number: DP83266VF
• Description: IC MEDIA ACSS CTRL INTF 160PQFP
• Manufacturer: National Semiconductor

Specifications of DP83266VF

• Applications: *
• Voltage - Supply: 4.75 V ~ 5.25 V
• Package / Case: 160-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83266VF

D2 –D0
D2 –D0
7 0 Control Information
Master Attention Register (MAR)
The Master Attention Register (MAR) collects enabled attentions from the State Attention Register Service Attention Register
No Space Attention Register Request Attention Register and Indicate Attention Register If the Notify bit in the Master Notify
Register and the corresponding bit in the MAR are set to One the INT1 pin is forced to LOW and thus triggers an interrupt
Writes to the Master Attention Register are permitted but do not change the contents
All bits in this register are set to Zero upon reset
Access Rules
Register Bits
Master Notify Register (MNR)
The Master Notify Register (MNR) is used to enable attentions in the Master Attention Register (MAR) If a bit in Register MNR
and the corresponding bit in Register MAR are set to One the INT1 signal is asserted to cause an interrupt
All bits in this register are set to Zero upon reset
Access Rules
Register Bits
Bit
D3
D4
D5
D6
D7
Bit
D3
D4
D5
D6
D7
STAN
STA
D7
D7
Address
Address
104h
105h
Symbol
RES
INA
RQA
SVA
NSA
STA
Symbol
RES
INAN
RQAN
SVAN
NSAN
STAN
NSAN
NSA
D6
D6
Reserved
Indicate Attention Register Is set if any bit in the Indicate Attention Register is set
Request Attention Register Is set if any bit in the Request Attention Register is set
Service Attention Register Is set if any bit in the Service Attention Register is set
No Space Attention Register Is set if any bit in the No Space Attention Register is set
State Attention Register Is set if any bit in the State Attention Register is set
Reserved
Indicate Attention Register Notify This bit is used to enable the INA bit in Register MAR
Request Attention Register Notify This bit is used to enable the RQA bit in Register MAR
Service Attention Register Notify This bit is used to enable the SVA bit in Register MAR
No Space Attention Register Notify This bit is used to enable the NSA bit in Register MAR
State Attention Register Notify This bit is used to enable the STA bit in Register MAR
Always
Always
Read
Read
SVAN
SVA
D5
D5
RQAN
RQA
(Continued)
D4
D4
Data Ignored
Always
Write
Write
INAN
INA
D3
D3
93
RES
RES
D2
D2
Description
Description
RES
RES
D1
D1
RES
RES
D0
D0