DP83266VF National Semiconductor, DP83266VF Datasheet - Page 73
DP83266VF
Manufacturer Part Number
DP83266VF
Description
IC MEDIA ACSS CTRL INTF 160PQFP
Manufacturer
National Semiconductor
Datasheet
1.DP83266VF.pdf
(152 pages)
Specifications of DP83266VF
Applications
*
Voltage - Supply
4.75 V ~ 5.25 V
Package / Case
160-BFQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Interface
-
Other names
*DP83266VF
- Current page: 73 of 152
- Download datasheet (2Mb)
D5 –D4
7 0 Control Information
Interrupt Condition Register (ICR)
The Interrupt Condition Register (ICR) collects unmasked interrupts from the Event Registers Interrupts are categorized into
Ring Events Token and Timer Events Counter Events and Error and Exceptional Status Events If the bit in the Interrupt Mask
Register (IMR) and the corresponding bit in the ICR are set to One the INT0 pin is forced low and thus triggers an interrupt
Note Bits are cleared ONLY by clearing underlying conditions (Mask bit and or Event Bit) in the appropriate Event Register
Access Rules
Register Bits
Bit
D7
D6
D3
D2
D1
D0
Address
ESE
02Eh
D7
Symbol
ESE
IERR
RES
COE
CIE
TTE
RNG
IERR
D6
Always
Read
Exception Status Event Interrupt Is set if any unmasked bits in the Exception Status Register are set
Internal Error Interrupt Is set if any bits in the Internal Event Register are set
Reserved
Counter Overflow Event Interrupt Is set if any unmasked bits in the Counter Overflow Latch Register
are set
Counter Increment Event Interrupt Is set if any unmasked bits in the Counter Increment Latch Register
are set
Token and Timer Event Interrupt Is set if any unmasked bits in the Token and Timer Event Latch
Register are set
Ring Event Interrupt Is set if any unmasked bits in the Ring Event Latch Registers are set
RES
D5
Data Ignored
Write
RES
(Continued)
D4
COE
D3
73
CIE
D2
Description
TTE
D1
RNG
D0
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