AD9887KS-100 Analog Devices Inc, AD9887KS-100 Datasheet - Page 37

• Manufacturer Part Number: AD9887KS-100
• Description: IC INTRFACE ANALOG/DVI 160-MQFP
• Manufacturer: Analog Devices Inc

Specifications of AD9887KS-100

• Rohs Status: RoHS non-compliant
• Applications: Graphic Cards, VGA Interfaces
• Interface: Analog and Digital
• Voltage - Supply: 3.15 V ~ 3.45 V
• Package / Case: 160-MQFP, 160-PQFP
• Mounting Type: Surface Mount

Write to four consecutive control registers
Read from one control register
Read from four consecutive control registers
Mux
Nos.
1 and 2
3
4
5, 6, and 7 11H: Bit 3
SCL
SDA
➥Start signal
➥Slave Address byte (R/W bit = LOW)
➥Base Address byte
➥Data byte to base address
➥Data byte to (base address + 1)
➥Data byte to (base address + 2)
➥Data byte to (base address + 3)
➥Stop signal
➥Start signal
➥Slave Address byte (R/W bit = LOW)
➥Base Address byte
➥Start signal
➥Slave Address byte (R/W bit = HIGH)
➥Data byte from base address
➥Stop signal
➥Start signal
➥Slave Address byte (R/W bit = LOW)
➥Base Address byte
➥Start signal
➥Slave Address byte (R/W bit = HIGH)
➥Data byte from base address
➥Data byte from (base address + 1)
➥Data byte from (base address + 2)
➥Data byte from (base address + 3)
➥Stop signal
Table LIV. Control of the Sync Block Muxes via the
Serial Register
BIT 7
Serial Bus
Control Bit
12H: Bit 4
12H: Bit 1
12H: Bit 2
SDA
SCL
BIT 6
t
BIT 5
t
STAH
BUFF
Control
Bit
State
0
1
0
1
0
1
0
1
BIT 4
BIT 3
t
Result
Pass Hsync
Pass Sync-on-Green
Pass Coast
Pass Vsync
Pass Vsync
Pass Sync Separator Signal
Pass Digital Interface Signals
Pass Analog Interface Signals
DHO
BIT 2
BIT 1
t
DAL
BIT 0
t
DAH
t
DSU
ACK
THEORY OF OPERATION (SYNC PROCESSING)
This section is devoted to the basic operation of the sync process-
ing engine (refer to Figure 37 Sync Processing Block Diagram).
Sync Slicer
The purpose of the sync slicer is to extract the sync signal from
the green graphics channel. A sync signal is not present on all
graphics systems, only those with “sync-on-green.” The sync
signal is extracted from the green channel in a two step process.
First, the SOG input is clamped to its negative peak (typically
0.3 V below the black level). Next, the signal goes to a compara-
tor with a trigger level that is 0.15 V above the clamped level.
The “sliced” sync is typically a composite sync signal containing
both Hsync and Vsync.
Sync Separator
A sync separator extracts the Vsync signal from a composite
sync signal. It does this through a low-pass filter-like or integrator-
like operation. It works on the idea that the Vsync signal stays
active for a much longer time than the Hsync signal, so it rejects
any signal shorter than a threshold value, which is somewhere
between an Hsync pulsewidth and a Vsync pulsewidth.
The sync separator on the AD9887 is simply an 8-bit digital
counter with a 5 MHz clock. It works independently of the
polarity of the composite sync signal. (Polarities are determined
elsewhere on the chip.) The basic idea is that the counter counts
up when Hsync pulses are present. But since Hsync pulses are
relatively short in width, the counter only reaches a value of N
before the pulse ends. It then starts counting down eventually
reaching 0 before the next Hsync pulse arrives. The specific
value of N will vary for different video modes, but will always be
less than 255. For example with a 1 µs width Hsync, the counter
will only reach 5 (1 µs/200 ns = 5). Now, when Vsync is present
on the composite sync the counter will also count up. However,
since the Vsync signal is much longer, it will count to a higher
number M. For most video modes, M will be at least 255. So,
Vsync can be detected on the composite sync signal by detecting
when the counter counts to higher than N. The specific count
that triggers detection (T) can be programmed through the
serial register (0fh).
Once Vsync has been detected, there is a similar process to detect
when it goes inactive. At detection, the counter first resets to 0,
then starts counting up when Vsync goes away. Similar to the
previous case, it will detect the absence of Vsync when the
counter reaches the threshold count (T). In this way, it will
reject noise and/or serration pulses. Once Vsync is detected to
be absent, the counter resets to 0 and begins the cycle again.
Write
t
STASU
t
STOSU
AD9887