N25Q128A11BF840F Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC., N25Q128A11BF840F Datasheet - Page 115

• Manufacturer Part Number: N25Q128A11BF840F
• Description: IC SRL FLASH 128MB NMX 8-VDFPN
• Manufacturer: Numonyx - A DIVISION OF MICRON SEMICONDUCTOR PRODUCTS, INC.
• Series: Forté™r

Specifications of N25Q128A11BF840F

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 108MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 1.7 V ~ 2 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VDFPN
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: N25Q128A11BF840F

9.2.1
DQ0
DQ1
S
C
1)
2)
Multiple I/O Read Identification protocol
The Multiple Input/Output Read Identification (MIORDID) instruction allows to read the
device identification data in the DIO-SPI protocol:
Unlike the RDID instruction of the Extended SPI protocol, the Multiple Input/Output
instruction can not read the Unique ID code (UID) (17 bytes).
For further details on the manufacturer and device identification codes please refer to
Section 9.1.1: Read Identification
Any Multiple Input/Output Read Identification (MIORDID) instruction while an Erase or
Program cycle is in progress, is not decoded, and has no effect on the cycle that is in
progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in parallel on the 2 pins DQ0 and DQ1. After this, the 24-bit
device identification, stored in the memory, will be shifted out on again in parallel on DQ1
and DQ0. Each two bits are shifted out during the falling edge of Serial Clock (C).
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Figure 44. Multiple I/O Read Identification instruction and data-out sequence DIO-
The number of Dummy Clock cycles is configurable by the user
SSE is only available in devices with Bottom or Top architecture.
–
–
Manufacturer identification (1 byte)
Device identification (2 bytes)
SPI
0
1
AFh
2
3
7
6
4
5
4
MAN.
code
(RDID).
5
3
2
6
1
0
7
7
6
8
5
4
DEV.
code
9 10 11 12 13 14 15
3
2
1
0
7
6
SIZE
code
Dual_Multi_Read_IO
5
4
3
2
1
0
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