NCN6804MNR2G ON Semiconductor, NCN6804MNR2G Datasheet - Page 20

• Manufacturer Part Number: NCN6804MNR2G
• Description: IC SMART CARD DUAL W/SPI 32-QFN
• Manufacturer: ON Semiconductor

Specifications of NCN6804MNR2G

• Applications: Smart Card
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Package / Case: 32-TFQFN Exposed Pad
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NCN6804MNR2G; NCN6804MNR2GOSTR

DC/DC Operation
able to handle either step up or step down power supply (see
CRD_VCCA or B to 400 mV called by the EMV
specifications, an active pull down NMOS is provided to
discharge the external CRD_VCCA/B reservoir capacitor.
This timing is guaranteed for a 10 mF maximum load
reservoir capacitor value (see Figure 4).
comments are referenced to Figures 16 and 17):
The power conversion is based on a full bridge structure
In order to achieve the 250 ms maximum time to discharge
The system operates with a two cycle concept (all
1. Cycle 1 Q1 and Q4 are switched ON and the
inductor L1 is charged by the energy supplied by
the external battery. During this phase, the pair
Q2/Q3 and the pair Q5/Q6 are switched OFF. The
current flowing the two MOSFET Q1 and Q4 is
internally monitored and will be switched OFF
when the I
programmed output voltage value) is reached. At
this point, Cycle 1 is completed and Cycle 2 takes
place. The ON time is a function of the battery
voltage and the value of the inductor network (L
CMD_STOP
CMD_1.8V
CMD_3.0V
CMD_5.0V
peak
value (depending upon the
10 mF
G_HIZ
G_Q1
G_Q3
G_Q4
G_Q2
G_Q7
C1
GND
Figure 16. Basic DC/DC Converter
Q3
Q1
http://onsemi.com
V
CC
20
Q5
Figure 16). The operation is fully automatic and, beside the
output voltage programming, does not need any further
adjustment.
(1.8 V, 3.0 V or 5.0 V), Q2 and Q3 are switched OFF
immediately to avoid over voltage on the output load. In the
meantime, the two extra NMOS Q5 and Q6 are switched ON
to fully discharge any current stored into the inductor,
avoiding ringing and voltage spikes over the system.
Figure 17 illustrates the theoretical waveforms present in
the DC/DC converter.
22 mH
L1
When the output voltage reaches the specified value
2. Cycle 2 Q2 and Q3 are switched ON and the
Q6
GND
PWR_GND
and Zr) connected across pins 10/11. A 4 _s
timeout structure ensures the system does run in a
continuous Cycle 1 loop.
energy stored into the inductor L1 is dumped into
the external load through Q2. During this phase,
the pair Q1/Q4 and the pair Q5/Q6 are switched
OFF. The current flow period is constant (900 ns
typical) and Cycle 1 repeats after this time if the
CRD_VCC voltage is below the specified value.
CRD_VCC
Q4
Q2
GND
Q7
C2
GND
10 mF