NCN6804MNR2G ON Semiconductor, NCN6804MNR2G Datasheet - Page 17

• Manufacturer Part Number: NCN6804MNR2G
• Description: IC SMART CARD DUAL W/SPI 32-QFN
• Manufacturer: ON Semiconductor

Specifications of NCN6804MNR2G

• Applications: Smart Card
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Package / Case: 32-TFQFN Exposed Pad
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NCN6804MNR2G; NCN6804MNR2GOSTR

B), the software has to poll the MISO register by sending a
MOSI A command (address {b7, b6, b5} = {0, X, 0})
followed by a MOSI B command (address {b7, b6, b5} = {0,
X, 1}) (or conversely). The corresponding MISO content
provides the previous state of the interface A or B that is the
{b1,b0} = {0,1}, {1,0} or {1,1}
Table 7. INTERRUPT RESET LOGIC TABLE
Table 8. INTERRUPT FUNCTION OPERATION
MOSI_b0
MOSI_b1
CRD_DET
In order to know the source of the interrupt (card A or card
Interrupt Source
(INT set to LOW)
T10
Card Extraction
T11
{b1,b0} = {0,0}
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Card Insertion
OVER LOAD
Over Load
CRD_VCC
INT
CS
A card has been inserted into the reader and detected by the CRD_DET signal. The NCN6001 pulls down the interrupt line.
The mC sets the CS signal to Low, the chip is now active, assuming the right address has been placed by the MOSI register.
The mC acknowledges the interrupt and resets the INT to High by the MOSI [B1 : B0 ] logic state: CRD_VCC is programmed
higher than zero volt.
The card has been extracted from the reader, CRD_DET goes Low and an interrupt is set (INT = L). On the other hand, the
PWR_DOWN sequence is activated by the NCN6001.
The interrupt pin is clear by the zero volt programmed to the interface.
Same as T0
The mC start the DC/DC converter, the interrupt is cleared (same as T2)
An overload has been detected by the chip : the CRD_VCC voltage is zero, the INT goes Low.
The card is extracted from the reader, CRD_DET goes Low and an interrupt is set (INT = L).
The card is re−inserted before the interrupt is acknowledged by the mC: the INT pin stays Low.
The mC acknowledges the interrupt and reset the INT to High by the MOSI [B1 : B0 ] logic state: CRD_VCC is programmed
higher than zero volt.
The Chip Select signal goes High, all the related NCN6001 interface(s) are deactivated and no further programming or
transaction can take place.
T0
CRD_VCC > 0 V
T1
CS
L
L
L
T2
Interrupt Clearance (INT reset to HIGH) CRD_VCCA/B / {b1, b0} pro-
CRD_VCC > 0 V
Figure 10. Basic Interrupt Function
T3
http://onsemi.com
T4
{0,1}, {1,0} or {11}
gramming
{0,0}
{0,0}
17
T5
information related to the cause of the interrupt. For each
case the MISO status obtained will be compared with the
MISO state prior to the interrupt. When 2 NCN6804 devices
share the same digital SPI bus, it is up to the software to poll
the devices using again the MISO register to identify the
reason of the interrupt.
T6
T7
T8
T9
T10
T11
Chip Address
{b7:b5} = 0XX
{b7:b5} = 0XX
{b7:b5} = 0XX
T12