NCN6804MNR2G ON Semiconductor, NCN6804MNR2G Datasheet - Page 11

• Manufacturer Part Number: NCN6804MNR2G
• Description: IC SMART CARD DUAL W/SPI 32-QFN
• Manufacturer: ON Semiconductor

Specifications of NCN6804MNR2G

• Applications: Smart Card
• Interface: 4-Wire SPI Serial
• Voltage - Supply: 2.7 V ~ 5.5 V
• Package / Case: 32-TFQFN Exposed Pad
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: NCN6804MNR2G; NCN6804MNR2GOSTR

Table 1. WRT_REG BIT DEFINITIONS
8. When operating in Asynchronous mode, b6 is compared with the external voltage level present pin S1 (Pin 1).
9. The CRD_RST pin reflects the content of the MOSI WRT_REG [b4] during the chip programming sequence. Since the bit shall be Low
b2
b3
b4
b5
b6
b7
to address the chip’s internal register, care must be observed as this signal will be immediately transferred to the CRD_RST pin.
If (b7 + b6 + b5 ) = 000 or (b7 + b6 + b5 ) = 010 then
Else if (b7 + b6 + b5 ) = 001 or (b7 + b6 + b5 ) = 011 then
Else if (b7 + b6 + b5) =110 or (b7 + b6 + b5) = 111 then
Else if (b7 + b6 + b5) =101 then
Else if (b7 + b6 + b5) =100 then
End if
If (b7 + b6 + b5) <> 101 and (b7 + b6 + b5) <> 100 then b4 Drives CRD_RSTA or B Pin
000
001
010
011
100
101
110
111
Case 00
Case 01
Case 10
Case 11
Case 00
Case 01
Case 10
Case 11
b3 drives CRD_CLKA or B (respectively)
b2 drives CRD_IOA or B (respectively)
Case 00
Case 01
Case 10
Case 11
NA (Not Applicable)
CRD_CLKA = CLK_IN
CRD_CLKA = CLK_IN / 2
CRD_CLKA = CLK_IN / 4
CRD_CLKB = Low
CRD_CLKB = CLK_IN
CRD_CLKB = CLK_IN / 2
CRD_CLKB = CLK_IN / 4
CRD_CLKA & B = SLO_SLP
CRD_CLKA & B = FST_SLP
NA
NA
Select NCN6804 device # 1 Asynchronous Card A (Note 8)
Select NCN6804 device # 1 Asynchronous Card B (Note 8)
Select NCN6804 device # 2 Asynchronous Card A (Note 8)
Select NCN6804 device # 2 Asynchronous Card B (Note 8)
NA
Select External Synchronous Card A
Select External Synchronous Card B
Set Card Detection Switch polarity, Set SPI_MODE normal or special , Set CRD_CLKA & B slopes Fast or Slow
CRD_CLKA = Low
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