NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet - Page 93
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NS7520B-1-C36
Manufacturer Part Number
NS7520B-1-C36
Description
IC ARM MICROPROCESSOR 177BGA
Manufacturer
Digi International
Series
NET+ARM®r
Specifications of NS7520B-1-C36
Applications
Network Processor
Core Processor
ARM7
Program Memory Type
External Program Memory
Controller Series
-
Ram Size
External
Interface
EBI/EMI, Ethernet, DMA, SPI, UART
Number Of I /o
16
Voltage - Supply
1.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
177-LFBGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NS7520B-1-C36
Manufacturer:
Digi International
Quantity:
10 000
Part Number:
NS7520B-1-C36
Manufacturer:
NETARM
Quantity:
20 000
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Interrupt controller registers
Interrupts come from different sources on the chip and are managed with Interrupt
Control registers. Interrupts can be enabled/disabled on a per-source basis using the
Interrupt Enable registers. These registers serve as masks for the different interrupt
sources.
Address: FFB0 0030 / 0034 / 0038
There are five pairs of registers in the interrupt controller:
Register bit assignment
All registers use the same 32-bit layout.
1 RX
SER
15
31
Interrupt Enable register. A read/write location for reading and writing all
interrupt enable bits as a typical register.
Interrupt Enable Set/Interrupt Status Enabled registers. Perform two
different functions depending on whether a register is read or written:
–
–
Interrupt Enable Clear/Interrupt Status Raw registers. Perform two
different functions depending on whether a register is read or written:
–
–
1 TX
SER
30
14
When read, the register indicates the current state of all enabled
interrupts.
When written, a 1 in a bit position sets that interrupt enable; a 0 in a bit
position has no effect.
When read, the register indicates the current state of all interrupts
regardless of the state of the enables.
When written, a 1 in a bit position clears that interrupt enable; a 0 in a bit
position has no effect.
2 RX
SER
29
13
2 TX
SER
28
12
27
11
26
10
Reserved
DMA1-13
25
9
24
8
MAC1
w w w . d i g i e m b e d d e d . c o m
23
7
Watch
Dog
22
6
Timer
21
5
1
Timer
20
4
2
PORT
19
C3
3
PORT
Rsvd
18
C2
2
G E N M o d u l e
ENET
PORT
1 RX
C1
17
1
PORT
ENET
1 TX
16
C0
0
8 1
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