NS7520B-1-C36 Digi International, NS7520B-1-C36 Datasheet - Page 187

• Manufacturer Part Number: NS7520B-1-C36
• Description: IC ARM MICROPROCESSOR 177BGA
• Manufacturer: Digi International
• Series: NET+ARM®r

Specifications of NS7520B-1-C36

• Applications: Network Processor
• Core Processor: ARM7
• Program Memory Type: External Program Memory
• Controller Series: -
• Ram Size: External
• Interface: EBI/EMI, Ethernet, DMA, SPI, UART
• Number Of I /o: 16
• Voltage - Supply: 1.4 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 177-LFBGA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 59: Ethernet Receive Status register bit definition
D10
D09
D08
D07
D06
Bits
R
R
R
R
R
Access
RXCRC
RXDR
RXCV
RXLNG
RXSHT
Mnemonic
0
0
0
0
0
Reset
Receive packet has CRC error
Set to 1 to indicate that the next packet in the receive FIFO
was received with a CRC error.
When this bit is set, the RXREGR and RXFIFOH bits in
the Ethernet General Status register remain inactive. The
bad receive packet is flushed immediately from the FIFO.
Receive packet has dribble bit error
Set to 1 to indicate that, at the end of the next packet in the
receive FIFO, an additional 1 to 7 bits of data (dribble
nibble) were received.
Note:
When this bit is set, the RXREGR and RXFIFOH bits in
the Ethernet General Status register remain inactive. The
bad receive packet is flushed immediately from the FIFO.
Receive packet has code violation
Set to 1 to indicate that the Ethernet PHY asserted the
RXER signal during the data phase of this frame. RXCV
indicates that the PHY encountered invalid receive codes
while receiving the data.
When this bit is set, the RXREGR and RXFIFOH bits in
the Ethernet General Status register remain inactive. The
bad receive packet is flushed immediately from the FIFO.
Receive packet is too long
Set to 1 to indicate that the next packet in the receive FIFO
is longer than 1518 bits. A long packet is accepted only
when the ERXLNG bit is set in the Ethernet General
Control register.
When this bit is set, the RXREGR and RXFIFOH bits in
the Ethernet General Status register remain inactive. The
bad receive packet is flushed immediately from the FIFO.
Receive packet is too short
Set to 1 to indicate that the next packet in the receive FIFO
is smaller than 64 bytes. A short packet is accepted only
when the ERXSHT bit is set in the Ethernet General
Control register.
When this bit is set, the RXREGR and RXFIFOH bits in
the Ethernet General Status register remain inactive. The
bad receive packet is flushed immediately from the FIFO.
Description
w w w . d i g i e m b e d d e d . c o m
This packet is considered valid if the RXCRC
bit (D10) is not set.
E t h e r n e t M o d u l e
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