W83627EHG Nuvoton Technology Corporation of America, W83627EHG Datasheet - Page 162

• Manufacturer Part Number: W83627EHG
• Description: IC I/O CONTROLLER 128-QFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83627EHG

• Applications: PC's, PDA's
• Interface: LPC
• Voltage - Supply: 3.3V
• Package / Case: 128-XFQFN
• Mounting Type: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.2.5
This register is used to control the FIFO functions of the UART.
Bit 6, 7: These two bits are used to set the active level of the receiver FIFO interrupt. The active level is
Bit 4, 5: Reserved
Bit 3: When this bit is set to logical 1, DMA mode changes from mode 0 to mode 1 if UFR bit 0 = 1.
Bit 2: Setting this bit to logical 1 resets the TX FIFO counter logic to its initial state. This bit is
Bit 1: Setting this bit to logical 1 resets the RX FIFO counter logic to its initial state. This bit is
Bit 0: This bit enables 16550 (FIFO) mode. This bit should be set to logical 1 before the other UFR bits
9.2.6
This register reflects the UART interrupt status.
the number of bytes that must be in the receiver FIFO to generate an interrupt.
BIT 7
automatically cleared afterwards.
automatically cleared afterwards.
are programmed.
UART FIFO Control Register (UFR) (Write only)
Interrupt Status Register (ISR) (Read only)
0
0
1
1
7
BIT 6
6
0
1
0
1
5
4
3
2
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
W83627EHF/EF, W83627EHG/EG
1
-151-
0
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
Publication Release Date: April 7, 2009
01
04
08
14
Version 1.94